张跃军

2026

基于对抗网络的可配置加解密硬件优化设计

《宁波大学学报(理工版)》

DOI

2026

MCDF: Structure-aware dual-domain anomaly detection for microscopic images of planar-gate SiC MOSFETs

Microelectronics Journal

DOI

2026

A low-power lightweight processor based on sparse convolutional neural network for wearable epilepsy detection devices

Microelectronics Journal

DOI

2026

RRAM-based gradient-aware victim row monitoring circuit for mitigating Rowhammer attacks

Integration

DOI

2026

FinSAA: Sparse-Aware CNN Accelerator With Fast Irregular Index Decoding and Adaptive Dense-Sparse Convolution Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

TQ-SPUF: A Software PUF Design Based on HEVC Transform and Quantization Module for Device Security and Video Anti-Tampering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

204-F2 leakage-based physically unclonable function with “zero” bit error rate through composite screening

Microelectronics Journal

DOI

2026

PAPS: A Power-Aware and Physically-Secure Cross-Domain Authentication Scheme for UAV-Assisted VANETs

IEEE Transactions on Dependable and Secure Computing

DOI

2026

Protecting the Information Security of Triboelectric Nanogenerator Devices in Industrial IoT Based on Physically Unclonable Function

IEEE Transactions on Industrial Informatics

DOI

2026

A high-reliability STT-MRAM PUF using a magnetoresistance sensing circuit with a time-domain bit-screening technique

Microelectronics Journal

DOI

2026

Bioinspired Ionochromic Neuromorphic Transistors for Robotic Intelligent Perception

Advanced Science

DOI

2026

Design of a configurable SoC for Alzheimer’s disease detection based on multimodal signals

BMC Bioinformatics

DOI

2026

A Low-Power 12-lead Arrhythmia Detection SoC Featuring a Reconfigurable CNN and Mixed-Precision Computing

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2026

Artificial Refractory Neuron Based on Cs 2 AgBiBr 6 Nanoionic Memristor for Efficient Motion Information Processing

Advanced Materials

DOI

2025

基于自检测修复的比特配置物理不可克隆函数电路设计

《电子与信息学报》

2025

STT-MRAM绝对差值原位计算驱动的轻量型AdderNet电路设计

《电子与信息学报》

2025

ATSS-PUF with hardware sharing for secure in-situ memory circuit

Integration

DOI

2025

A High-Precision Third-Order Sigma–Delta Modulator Circuit Design

Journal of Circuits Systems and Computers

DOI

2025

Nonvolatile Optical Switch With a Programmable p-n Heterojunction

IEEE Transactions on Electron Devices

DOI

2025

A RRAM-based logic in memory DES implementation against power attacks

Microelectronic Engineering

DOI

2025

Quantized conductance in MoS2 memristors for high-accuracy neuromorphic computing

Journal of Physics D Applied Physics

DOI

2025

A Strong PUF-Based Security Protocol to Protect AI Model Parameters Against Privacy Information Leakage

IEEE Internet of Things Journal

DOI

2025

Improving the Stability of APUF to 100% Without Extra Hardware Overhead for Enhancing the Performance of Security Authentication Protocols

IEEE Internet of Things Journal

DOI

2025

High-Precision Attention Mechanism for Machine Vision Enabled by an Artificial Optoelectronic Memristor Synapse

Nano Letters

DOI

2025

A Hierarchical Cooperative Authentication Protocol for Attack-Resilient UAV Swarms With Ultra-Low Overhead

IEEE Transactions on Information Forensics and Security

DOI

2025

A Lightweight Arbiter PUF Design Based on Threshold Loss in Transmission Gates

IEEE International Conference on ASIC (ASICON)

DOI

2025

Design of Secure Storage Circuit Based on Reversible Logic XOR-Toffoli Gate

IEEE International Conference on ASIC (ASICON)

DOI

2025

ADC-Free RRAM-Based XNOR-Bitcount Architecture for Hand Gesture Recognition

IEEE International Conference on ASIC (ASICON)

DOI

2025

A Real-Time and Reconfigurable Pre-Driver Design for ABS Solenoid Valve Applications

IEEE International Conference on ASIC (ASICON)

DOI

2025

Real-Time Highly Flexible Wheel Speed Sensing Interface IP Design

IEEE International Conference on ASIC (ASICON)

DOI

2024

基于后量子密码算法的安全SoC芯片设计

《集成电路与嵌入式系统》

2024

A Lightweight Folded Keccak-Based SHA-3 for Resource-Constrained Embedded Security

IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

DOI

2024

An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit

Integration

DOI

2024

A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2024

Reconfigurable Low-Overhead SoC for Arrhythmia Detection Based on Cyclic Convolutional Neural Networks

International Conference on Integrated Circuits and Microsystems (ICICM)

DOI

2024

A Power Balanced Against Side Channel Attack SM4 Algorithm Based on RRAM/CMOS Hybrid Technology

International Conference on Integrated Circuits and Microsystems (ICICM)

DOI

2024

Secure Encryption and Decryption Circuit on 8T1C Structure-Based Charge Accumulation and Dissipation

International Conference on Integrated Circuits and Microsystems (ICICM)

DOI

2024

A Defense Against Rowhammer Attacks Based on Dual-Layer RRAM Counting Method

International Conference on Integrated Circuits and Microsystems (ICICM)

DOI

2024

Design of Medical Privacy Protection Circuit Based on Cross Obfuscation

International Conference on Integrated Circuits and Microsystems (ICICM)

DOI

2024

Lightweight skin cancer detection IP hardware implementation using cycle expansion and optimal computation arrays methods

Computers in Biology and Medicine

DOI

2024

DSP-PUF: A Software PUF Based on Digital Signal Processor for IoT Security

DOI

2024

A High-Performance MTJ-LUT Circuit Using 4T1M Architecture

DOI

2024

A Reliable Current Starved Inverter PUF Based on SRAM Memory Structure

DOI

2024

A Hybrid-Logic Scheme for High-Performance and Low-Power Decoders in 7nm Process

DOI

2024

A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2024

Gas Sensor Physically Unclonable Function-Based Lightweight Bidirectional Authentication Protocol for Gas Sensor Networks

Electronics

DOI

2024

A True Random Number Generator Design Based on the Triboelectric Nanogenerator with Multiple Entropy Sources

Micromachines

DOI

2024

An efficient ANN SoC for detecting Alzheimer's disease based on recurrent computing

Computers in Biology and Medicine

DOI

2024

A Physical Unclonable Function Feature Extraction Technique for Oil Paintings Copyright Protection

IEEE International Test Conference in Asia (ITC-Asia)

DOI

2024

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Microelectronics Journal

DOI

2024

High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

Integration

DOI

2024

Novel crosstalk circuit design for high density logic applications

Microelectronics Journal

DOI

2024

Highly Reliable RS-PUF Based on Reconfigurable Gas Sensor Array

IEEE Sensors Journal

DOI

2024

A Novel DES Encryption Circuit Based on RRAM XOR Gates

DOI

2023

基于ZnO忆阻器的高鲁棒性毛刺型物理不可克隆函数设计

《电子与信息学报》

2023

基于隧穿磁阻磁强计的软物理不可克隆函数设计

《电子与信息学报》

2023

SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2023

Full-custom Design of Improved Carry Adder Circuit for CLBs

IEEE International Conference on ASIC (ASICON)

DOI

2023

High-Performance Rejection Sampling Hardware Circuit Design for Kyber

IEEE International Conference on ASIC (ASICON)

DOI

2023

An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process

IEEE International Conference on ASIC (ASICON)

DOI

2023

Highly Reliable Physical Unclonable Function Based on ZnO-SnO2 Gas Sensor

IEEE International Conference on ASIC (ASICON)

DOI

2023

Ternary Multiply-Accumulate Circuit Based on Domino Structure

IEEE International Conference on ASIC (ASICON)

DOI

2023

An Efficient Hash Computing Unit for Kyber Algorithm

IEEE International Conference on ASIC (ASICON)

DOI

2023

A 7nm-Based Decodable Self-Resetting Regfile Circuit

IEEE International Conference on ASIC (ASICON)

DOI

2023

Design of High-Performance Gas-Sensing PUF Based on Nanoparticles/Fibers With Composite Morphology

IEEE Sensors Journal

DOI

2023

High-Directionality Silicon Nitride Antenna Based on Distributed Bragg Reflector for Optical Phased Array

Photonics

DOI

2023

Profiling side-channel attacks based on CNN model fusion

Microelectronics Journal

DOI

2023

Hardware Design and Implementation of a Lightweight Saber Algorithm Based on DRC Method

Electronics

DOI

2023

Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction

Microelectronics Journal

DOI

2023

Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers

IEEE Transactions on Circuits and Systems I Regular Papers

DOI

2023

Design of Interface Circuits and Lightweight PUF for TMR Sensors

IEEE Sensors Journal

DOI

2023

Near‐Sensor Reservoir Computing for Gait Recognition via a Multi‐Gate Electrolyte‐Gated Transistor

Advanced Science

DOI

2023

A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection

Computers in Biology and Medicine

DOI

2023

On-chip Ce:YIG/Si Mach–Zehnder optical isolator with low power consumption

Optics Express

DOI

2023

Optogenetics-inspired manipulation of synaptic memory using all-optically controlled memristors

Nanoscale

DOI

2023

A 7‐nm‐Based 5R4W High‐Timing Reliability Regfile Circuit

IET Circuits Devices & Systems

DOI

2022

基于忆阻器的多模式识别CNN电路设计

《实验技术与管理》

2022

基于线性无关矩阵的按需解锁硬件混淆方法

《电子学报》

2022

PI PUF: A Processor-Intrinsic PUF for IoT

Computers & Electrical Engineering

DOI

2022

Reservoir Computing-Based Design of ZnO Memristor-Type Digital Identification Circuits

Micromachines

DOI

2022

A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices

Microelectronics Journal

DOI

2022

Temporal Pattern Coding in Ionic Memristor‐Based Spiking Neurons for Adaptive Tactile Perception

Advanced Electronic Materials

DOI

2022

A configurable detection chip with ±0.6% Inaccuracy for liquid conductivity using dual-frequency sinusoidal signal technique in 65 nm CMOS

Microelectronics Journal

DOI

2022

A 65nm/0.448 mW EEG processor with parallel architecture SVM and lifting wavelet transform for high-performance and low-power epilepsy detection

Computers in Biology and Medicine

DOI

2022

An ACF<0.03 low-power software PUF based on the RISC-V processor for IoT security

Microelectronics Journal

DOI

2022

A flexible dual-gate hetero-synaptic transistor for spatiotemporal information processing

Nanoscale Advances

DOI

2021

A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States

IEEE International Conference on ASIC (ASICON)

DOI

2021

A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security

IEEE International Conference on ASIC (ASICON)

DOI

2021

A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power

IEEE International Conference on ASIC (ASICON)

DOI

2021

A Multi-conductance States Memristor-based CNN Circuit Using Quantization Method for Digital Recognition

IEEE International Conference on ASIC (ASICON)

DOI

2021

A String-in-string-out 256 Bits eFuse Using Full-custom Design in 55nm Process

IEEE International Conference on ASIC (ASICON)

DOI

2021

A HfO2 Ferroelectric Capacitor based 10T2C High Reliability Non-Volatile SRAM for Low Power IoT Applications

IEEE International Conference on ASIC (ASICON)

DOI

2021

A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger

IEEE International Conference on ASIC (ASICON)

DOI

2021

A Quantized Convolutional Neural Network Implemented With Memristor for Image Denoising and Recognition

Frontiers in Neuroscience

DOI

2021

TVD‐PB logic circuit based on camouflaging circuit for IoT security

IET Circuits Devices & Systems

DOI

2021

SPUF design based on Camellia encryption algorithm

Microelectronics Journal

DOI

2021

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

Integration

DOI

2020

Orthogonal obfuscation based key management for multiple IP protection

Integration

DOI

2020

A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

A Low Cost MST-FSM Obfuscation Method for Hardware IP Protection

Journal of Circuits Systems and Computers

DOI

2020

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

IET Circuits Devices & Systems

DOI

2020

Design of SH Aging Sensor for Real Time and Application in Sensing Network

Canadian Journal of Electrical and Computer Engineering

DOI

2019

基于二相滤波的可重构光学物理不可克隆函数设计

《光子学报》

2019

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key

IEEE Asian Solid-State Circuits Conference (A-SSCC)

DOI

2019

A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor

IEEE International Conference on ASIC (ASICON)

DOI

2019

PbS Quantum Dots Based on Physically Unclonable Function for Ultra High-Density Key Generation

Journal of Electronic Materials

DOI

2019

Implementation of All 27 Possible Univariate Ternary Logics With a Single ZnO Memristor

IEEE Transactions on Electron Devices

DOI

2019

Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias

Microelectronics Journal

DOI

2019

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2019

A univariate ternary logic and three-valued multiplier implemented in a nano-columnar crystalline zinc oxide memristor

RSC Advances

DOI

2018

基于忆阻器的SIMON轮函数电路设计

《宁波大学学报(理工版)》

2018

Design of Delayed Ternary PUF Circuit Based on CNFET

Asia-Pacific Conference on Communications (APCC)

DOI

2018

Detecting the Control Flow Attacks Based on Built-in Secure Register Bank

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2018

Obfuscation Algorithm Design Based on Fully Homomorphism

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2018

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Journal of Semiconductors

DOI

2017

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

Journal of Semiconductors

DOI

2017

A multi-port low-power current mode PUF using MOSFET current-division deviation in 65 nm technology

Microelectronics Journal

DOI

2017

Design Impedance Mismatch Physical Unclonable Functions for IoT Security

Active and Passive Electronic Components

DOI

2016

基于信号传输理论的Glitch物理不可克隆函数电路设计

《电子与信息学报》

2016

A ternary polarity conversion technique for fixed polarity Reed-Muller expansions

IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

DOI

2016

DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation

IEEE Computer Society Annual Symposium on VLSI

DOI

2015

基于最优控制电压的高鲁棒性PUF电路设计

《电子学报》

2015

Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS

IEEE International Conference on ASIC (ASICON)

DOI

2015

A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS

International Journal of Electronics

DOI

2015

Design of a reliable PUF circuit based on R–2R ladder digital-to-analog convertor

Journal of Semiconductors

DOI

2014

Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS

International Symposium on Integrated Circuits

DOI

2014

Design of lightweight PUF circuit based on selectable cross-coupled inverters

Journal of Electronics (China)

DOI

2014

Design of anti-distinguish attack for SHA-3 algorithm based on improved cp-kernel

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2014

Design of compact CN delay-based PUFS in 65nm CMOS

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2014

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

IEICE Electronics Express

DOI

2013

Highly stable data SRAM-PUF in 65nm CMOS process

IEEE International Conference on ASIC (ASICON)

DOI

2013

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65nm CMOS

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2013

Design of current type PUF based on current mirror

Journal of Circuits and Systems

2012

防御零值功耗攻击的AES SubByte模块设计及其VLSI实现

《电子学报》

2012

Model and physical implementation of multi-port PUF in 65 nm CMOS

International Journal of Electronics

DOI

2012

Robust and low power register file in 65 nm technology

Journal of Semiconductors

DOI

2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

IEICE Electronics Express

DOI

2012

Design of a high information-density multiple valued 2-read 1-write register file

IEICE Electronics Express

DOI

2012

Design of AES SubByte Module of Anti-Zero Value Power Attack and Its VLSI Implementation

Dianzi xuebao

2011

Design of resistant DPA three-valued counter based on SABL

IEEE International Conference on ASIC (ASICON)

DOI

2010

Design of multi-valued counter based on νMOS

Journal of Circuits and Systems

2009

Design of multi-valued double-edge-triggered JK flip-flop based on neuron MOS transistor

IEEE International Conference on ASIC (ASICON)

DOI

2009

Design of Four-Valued Operation Circuits of Adder and Subtraction Based on Neuron MOS Transistor

DOI

2017

Design of ternary pulsed reversible counter based on CNFET

IEEE International Conference on ASIC (ASICON)

DOI

2017

A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification

IEEE International Conference on ASIC (ASICON)

DOI

2016

Design a delay amplified digital aging sensor circuit in 65nm CMOS

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2023

High-Efficiency focusing grating coupler with distributed Bragg reflector

DOI

2017

Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation

Springer eBooks

DOI