杜力｜南京大学｜学者主页

2026

SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention

Wen-Tao Xu, Yuxuan Zhang, Rong-Zhou Zhu, Xiang Wu, Ze-Hao Wang, Wei-Lin Li, Jia-Xiang Wang, Chun-Yang Du, Yuan-Lu Gao, Zhan-Xiang Gao, Feng-Dong Qu, Jin-Ming Lu, Li Du

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

MG-PM: A Mixed-Granularity Polynomial Multiplier for High-Efficient Computation Across Variable Degrees

Yiping Shi, Liulu He, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

A Compilation Framework for Domain Specific Multi-Chiplet Systems with Double-Layer Genetic Algorithms

Qi Wu, Yichuan Bai, Chao-Ming Fang, Yuan Du, Li Du

International Symposium on Circuits and Systems

DOI

2026

A 2D-DCT Processor Using One-Time-Programmed Floating-Gate Transistor Array for Processing-in-Sensor Architecture

Junshu Shen, Ye Lin, Wei Jiang, Da-Wei Li, Yuan Du, Li Du, Jing-Jing Lv

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

CVFFA: A Convolution and Variable-Size FFT Fusion Accelerator for rPPG-Based Non-Contact Heart Rate Detection

Chenjia Xie, Zhuang Shao, Chengrui Li, Yajie Wu, Chong-Kang Tan, Yuan Du, Li Du

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

UniMAC: Multi-Precision MAC with a Unified Computing Architecture for Efficient Large Language Model Inference

Xiao Cong, Xingyuan Hu, Juntao Liu, Xulong Zhang, Hao-Ran Geng, Qi Wu, Yuan Du, Li Du

International Symposium on Circuits and Systems

DOI

2026

A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network

Aojie Jiang, K. Zhu, Zhi-Heng Zhang, Zhe Su, Juntao Liu, Yuan Du, Li Du

arXiv.org

DOI

2026

A Scheduling Framework for Efficient MoE Inference on Edge GPU-NDP Systems

Qi Wu, Chao Fang, Jiayuan Chen, Ye Lin, Yueqi Zhang, Yichuan Bai, Yuan Du, Li Du

Design, Automation and Test in Europe

DOI

2026

CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device

Ye Lin, Chao Fang, Xiaoyong Song, Qi Wu, Anying Jiang, Yichuan Bai, Li Du

DOI

2025

高效Winograd卷积硬件设计及其量化方案

严峥，张宸硕，白一川，杜源，杜力

《集成电路与嵌入式系统》

DOI

2025

BE-NPU: A Bandwidth-Efficient Neural Processing Unit With Adaptive Processing Schemes for Reduced Off-Chip Bandwidth Demand

Yichuan Bai, Xiaopeng Zhang, Qian Wang, Yaqing Li, Yuan Du, Li Du

IEEE transactions on computers

DOI

2025

A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations

Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2025

Corrections to "An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks"

Heng Zhang, W. Yin, Sunan He, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2025

KV Cache Compression Based on Token-Level Redundancy Elimination and Bit-Level Encoding

Tianze Li, Chenjia Xie, Jiayuan Chen, Yuan Du, Li Du

International Conference on Artificial Intelligence Circuits and Systems

DOI

2025

An Efficient Accelerator for Attention Mechanism Based on Combined-Head Low-Rank Projection and Unified-PE Candidate Selection

Xingyuan Hu, Xulong Zhang, Xiao Cong, Hao-Ran Geng, Chong-Kang Tan, Yuan Du, Li Du

Asia Pacific Conference on Circuits and Systems

DOI

2025

A Hybrid-Structured Lossless Compression–Decompression Engine for Intermediate Feature Maps in Vision Neural Networks

Junyong Hua, Hang Xu, Yichuan Bai, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2025

FBQuant: FeedBack Quantization for Large Language Models

Yijiang Liu, Hengyu Fang, Liulu He, Rongyu Zhang, Yichuan Bai, Yuan Du, Li Du

International Joint Conference on Artificial Intelligence

DOI

2025

CLCO-S1: Efficient Softmax1 Architecture of Cross Level Collaborative Optimization for Transformer

Ying-Qian Chen, Hao-Ran Geng, Cheng Liu, Li Du

Asia Pacific Conference on Circuits and Systems

DOI

2025

RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory

Chenjia Xie, Zhuang Shao, Ming-Zhe Zhang, Yuan Du, Li Du

IEEE Journal of Solid-State Circuits

DOI

2024

AICAS Grand Challenge 2024: Software and Hardware Co-optimization for General Large Language Model Inference on CPU

Junfeng Tan, Guosheng Yu, Jia-Ning Li, Xiao-Han Ma, Fan Bao, Evens Pan, David Bian, Yong-Fu Li, Yuan Du, Li Du, Bo Li, Wei Mao

International Conference on Artificial Intelligence Circuits and Systems

DOI

2024

An Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary Shapes

Yichuan Bai, Xiaopeng Zhang, Qian Wang, Jing-Jing Lv, Lei Chen, Yuan Du, Li Du

International Conference on Artificial Intelligence Circuits and Systems

DOI

2024

A Streaming Transformer Accelerator with Efficient On-Chip Normalization

Ning Zhao, Jiayuan Chen, Jing-Jing Lv, Chenjia Xie, Yuan Du, Li Du

Asia Pacific Conference on Circuits and Systems

DOI

2024

A Resource-Efficient Weight Quantization and Mapping Method for Crossbar Arrays in ReRAM-based Computing-in-Memory Systems

Mingyuan Ma, Wei Jiang, Juntao Liu, Li Du, Zhongyuan Ma, Yuan Du

Asia Pacific Conference on Circuits and Systems

DOI

2024

SFC: Achieve Accurate Fast Convolution under Low-precision Arithmetic

Liulu He, Yu-Fei Zhao, Rui Gao, Yuan Du, Li Du

International Conference on Machine Learning

DOI

2024

An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction

Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2024

An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction

Zhuang Shao, Chenjia Xie, Zihan Ning, Qi Wu, Liang Chang, Yuan Du, Li Du

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2024

An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks

Heng Zhang, W. Yin, Sunan He, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2024

Linearity Performance of Charge Domain In-memory Computing: Analysis and Calibration

Heng Zhang, Yichuan Bai, Jun-Jie Shen, Yuan Du, Li Du

Integrated Circuits and Systems

DOI

2024

GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators

Aojie Jiang, Li Du, Yuan Du

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2024

An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling

Chengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du

Asia Pacific Conference on Circuits and Systems

DOI

2024

Improved JPEG Lossless Compression for Compression of Intermediate Layers in Neural Networks Based on Compute-In-Memory

Junyong Hua, Hang Xu, Yuan Du, Li Du

Electronics

DOI

2024

Optoelectronic Computing Evaluation and Deployment Platform Based on a 256-MAC Silicon Photonic Chip

Li-Kai Li, Yichuan Bai, Shengping Liu, Yang Zhao, Sunan He, Yaqing Li, Li Du, Yuan Du

International Symposium on Circuits and Systems

DOI

2024

An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage

Ye Lin, Yuandong Li, Heng Zhang, He Ma, Jing-Jing Lv, Anying Jiang, Yuan Du, Li Du

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2024

A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction

Yichuan Bai, Yaqing Li, Heng Zhang, Aojie Jiang, Yuan Du, Li Du

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2023

Linearity Analysis for Charge Domain In-memory Computing

Heng Zhang, Yuan Du, Li Du

International Conference on ASIC

DOI

2023

Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators

Hang Xu, Chenjia Xie, Xin Lu, Li Du, Yuan Du

International Conference on ASIC

DOI

2023

An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects

Yajie Wu, Tianze Li, Zhuang Shao, Li Du, Yuan Du

International Conference on Artificial Intelligence Circuits and Systems

DOI

2023

An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression

Chenjia Xie, Zhuang Shao, Ning Zhao, Yuan Du, Li Du

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2023

QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations

Hao-Ran Geng, Xiaoliang Chen, Ning Zhao, Yuan Du, Li Du

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2023

Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping

Yichuan Bai, Zhuang Shao, Chenshuo Zhang, Aojie Jiang, Yuan Du, Li Du

International Conference on Artificial Intelligence Circuits and Systems

DOI

2023

SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference

Heng Zhang, Su He, X. Lu, Xin-Jie Guo, Shao-Di Wang, Yuan Du, Li Du

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2023

Grand Challenge on Software and Hardware Co-Optimization for E-Commerce Recommendation System

Jianing Li, Jia-Bin Liu, Xingyuan Hu, Yuhang Zhang, Guosheng Yu, Shi-Meng Qian, Wei Mao, Li Du, Yongfu Li, Yuan Du

International Conference on Artificial Intelligence Circuits and Systems

DOI

2023

CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification

Lirui Xiao, Huanrui Yang, Zhen Dong, Kurt Keutzer, Li Du, Shanghang Zhang

Proceedings - ACM IEEE Design Automation Conference

DOI

2022

SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access

Xingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du

International SoC Design Conference

DOI

2022

A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system

Xuewen He, Yajie Wu, Yichuan Bai, Jie Liu, Li Du, Yuan Du

International Symposium on Embedded Multicore/Many-core Systems-on-Chip

DOI

2022

Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting

Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang

IEEE International Symposium on Circuits and Systems proceedings

DOI

2021

CTT-based Non-Volatile Deep Neural Network Accelerator Design

Yang Xiao, Wuyu Fan, Yuan Du, Li Du, M. Chang

International SoC Design Conference

DOI

2021

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression

Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Weihao Zhuang, Huadong Wei, Chenjia Xie, Zhong-Feng Wang

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2021

LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator

Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang

International SoC Design Conference

DOI

2021

Flexible-width Bit-level Compressor for Convolutional Neural Network

Junhan Zhu, Xiaoliang Chen, Li Du, Haoran Geng, Yichuan Bai, Yuandong Li, Yuan Du, Zhongfeng Wang

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

DOI

2021

A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference

Kai Chen, Yimin Huang, Yuan Du, Zhuang Shao, Xingyu Gu, Li Du, Zhongfeng Wang

IEEE International Symposium on Circuits and Systems proceedings

DOI

2020

A Reconfigurable 64-Dimension K-Means Clustering Accelerator With Adaptive Overflow Control

Li Du, Yuan Du, M. Chang

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2020

In-Memory Computing: The Next-Generation AI Computing Paradigm

Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang

DOI

2019

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks

Meiqi Wang, Jianqiao Mo, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International Workshop on Signal Processing Systems (SiPS)

DOI

2019

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding

Siyuan Lu, Jinming Lu, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International Workshop on Signal Processing Systems (SiPS)

DOI

2019

EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing

Wenjian Liu, Xiayuan Wen, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International Workshop on Signal Processing Systems (SiPS)

DOI

2019

Training Deep Neural Networks Using Posit Number System

Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International System-on-Chip Conference (SOCC)

DOI

2017

Hardware Accelerator Design for Machine Learning

Li Du, Yuan Du

Machine-mediated learning

DOI

2017

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Li Du, Yuan Du, Yi-Lei Li, Junjie Su, Yen-Cheng Kuan, Chun-Chen Liu, M. Chang

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

RAM-NAF: A Reconfigurable Analog Module for Nonlinear Activation Function Computation in Processing-in-Memory

Chenjia Xie, Zhuang Shao, Yajie Wu, Cheng-Jie Liu, Ming-Zhe Zhang, Yuan Du, Li Du, C. H

精选作品

期刊论文

SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention

MG-PM: A Mixed-Granularity Polynomial Multiplier for High-Efficient Computation Across Variable Degrees

A Compilation Framework for Domain Specific Multi-Chiplet Systems with Double-Layer Genetic Algorithms

A 2D-DCT Processor Using One-Time-Programmed Floating-Gate Transistor Array for Processing-in-Sensor Architecture

CVFFA: A Convolution and Variable-Size FFT Fusion Accelerator for rPPG-Based Non-Contact Heart Rate Detection

UniMAC: Multi-Precision MAC with a Unified Computing Architecture for Efficient Large Language Model Inference

A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network

A Scheduling Framework for Efficient MoE Inference on Edge GPU-NDP Systems

CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device

高效Winograd卷积硬件设计及其量化方案

BE-NPU: A Bandwidth-Efficient Neural Processing Unit With Adaptive Processing Schemes for Reduced Off-Chip Bandwidth Demand

A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations

Corrections to "An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks"

KV Cache Compression Based on Token-Level Redundancy Elimination and Bit-Level Encoding

An Efficient Accelerator for Attention Mechanism Based on Combined-Head Low-Rank Projection and Unified-PE Candidate Selection

A Hybrid-Structured Lossless Compression–Decompression Engine for Intermediate Feature Maps in Vision Neural Networks

FBQuant: FeedBack Quantization for Large Language Models

CLCO-S1: Efficient Softmax1 Architecture of Cross Level Collaborative Optimization for Transformer

RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory

AICAS Grand Challenge 2024: Software and Hardware Co-optimization for General Large Language Model Inference on CPU

An Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary Shapes

A Streaming Transformer Accelerator with Efficient On-Chip Normalization

A Resource-Efficient Weight Quantization and Mapping Method for Crossbar Arrays in ReRAM-based Computing-in-Memory Systems

SFC: Achieve Accurate Fast Convolution under Low-precision Arithmetic

An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction

An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction

An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks

Linearity Performance of Charge Domain In-memory Computing: Analysis and Calibration

GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators

An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling

Improved JPEG Lossless Compression for Compression of Intermediate Layers in Neural Networks Based on Compute-In-Memory

Optoelectronic Computing Evaluation and Deployment Platform Based on a 256-MAC Silicon Photonic Chip

An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage

A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction

Linearity Analysis for Charge Domain In-memory Computing

Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators

An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects

An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression

QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations

Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping

SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference

Grand Challenge on Software and Hardware Co-Optimization for E-Commerce Recommendation System

CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification

SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access

A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system

Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting

CTT-based Non-Volatile Deep Neural Network Accelerator Design

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression

LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator

Flexible-width Bit-level Compressor for Convolutional Neural Network

A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference

A Reconfigurable 64-Dimension K-Means Clustering Accelerator With Adaptive Overflow Control

In-Memory Computing: The Next-Generation AI Computing Paradigm

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding

EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing

Training Deep Neural Networks Using Posit Number System

Hardware Accelerator Design for Machine Learning

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

RAM-NAF: A Reconfigurable Analog Module for Nonlinear Activation Function Computation in Processing-in-Memory

研究方向