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2026

A 16-Bit High-Accuracy R-2R DAC Using Auxiliary-DAC-Assisted Bit-by-Bit Calibration

Yidan Zhang, Lei Qiu, Jiangfan Wen

Conference proceedings

DOI

2026

A 14-b 65.3-dB SNDR 200-MS/s Coarse-fine SAR ADC with Rail-to-Rail Input Common Mode Range in 28-nm CMOS

Jiangfan Wen, HaoLi Hu, Hui Zhang, Bingbing Yao, Lei Qiu

Circuits Systems and Signal Processing

DOI

2026

A 13-b 320-MS/s Noise-Successive-Attenuated SAR ADC with R-C-Traded-Off Reference Buffer

Jiangfan Wen, Qide Cheng, Shenglong Zhuo, Miao Meng, Hui Zhang, Bingbing Yao, Lei Qiu

IEEE Custom Integrated Circuits Conference (CICC)

DOI

2026

A 150-Msps 77-dB SNDR SAR ADC in 28-nm CMOS

Bingbing Yao, Jiangfan Wen, Likai Shen, Qide Cheng, Miao Meng, Hui Zhang, Lei Qiu

IEEE Custom Integrated Circuits Conference (CICC)

DOI

2025

A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS

Hui Zhang, Yong Li, Dawei Dong, Danben He, Yuan Gao, Jing Jin, Yuekang Guo, Lei Qiu, Zhenrong Li, Lin Cheng

Microelectronics Journal

DOI

2024

A 16-Bit 1.6-kS/s ΔΣ Modulator Based on Folded-Cascode Dynamic Amplifier With Speed Enhancement and PVT-Tracking Techniques

Yifu Guo, Zhongxiao Tian, Likai Shen, Hanbo Yu, Lei Qiu, Bingbing Yao

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2024

A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs

Hui Hu, Bingbing Yao, Yi Shan, Lei Qiu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2024

A Reference Assisted Background Calibration Technique With Constant Input Impedance for Time-Interleaved ADCs

Wenli Xu, Bingbing Yao, Qide Cheng, Zihao Du, Lei Qiu

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2023

A Boundary Mixing Architecture for Two-Channel Frequency-Interleaving Analog-to-Digital Converters

Wenli Xu, Zihao Du, Lei Qiu

IEEE Access

DOI

2023

A Output Code Density Histograms Based Calibration Algorithm of Capacitor Mismatch for SAR ADC

Hui Hu, Lei Qiu, Bingbing Yao

IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

DOI

2023

A Speed-Enhancement Technique Based on Single-Node-Detection and Bulk-Driven for Inverter-Based Amplifier in Switched-Capacitor Integrator

Yifu Guo, Lei Qiu

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2023

Capacitor Mismatch Calibration of a 16-Bit SAR ADC Using Optimized Segmentation and Shuffling Scheme

Zihao Du, Bingbing Yao, Wenli Xu, Xiaopan Wang, Hui Hu, Lei Qiu

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2023

A Low-Power Common-Mode Detector with PVT-Compensation Technique for Dynamic Amplifier in Delta-Sigma Modulator

Yifu Guo, Lei Qiu

Circuits Systems and Signal Processing

DOI

2022

A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs

Lei Qiu, Tianyi Meng, Bingbing Yao, Zihao Du, Xiaohua Yuan

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2022

A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

Bingbing Yao, Lei Qiu

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2022

A Highly Area-Efficient Switching Scheme based on Charge Sharing and Capacitor Holding for SAR ADCs

Yifu Guo, Lei Qiu, Bingbing Yao

Circuits Systems and Signal Processing

DOI

2021

A 98.6 dB SNDR SAR ADC With a Mismatch Error Shaping Technique Implemented With Double Sampling

Chuanshi Yang, Lei Qiu, Kai Tang, Yuanjin Zheng

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2021

An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

Chuanshi Yang, Erik Olieman, Alphons Litjes, Lei Qiu, Kai Tang, Yuanjin Zheng, Robert van Veldhoven

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

A High-Speed Low-Power Flash ADC with Continued Pipelined Gating in 28-nm CMOS

Yu Miao Gao, Lei Qiu, Xin Yu Guo, Mei Song Tong

IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization

DOI

2020

A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

Zhenwei Zhang, Lei Qiu, Yi Shan, Yemin Dong

IEICE Electronics Express

DOI

2020

Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators

Jie Sun, Minglei Zhang, Lei Qiu, Jianhui Wu, Weiqiang Liu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs

Lei Qiu, Keping Wang, Chuanshi Yang, Yuanjin Zheng

IEEE Access

DOI

2019

A High-gain High-precision Dynamic Comparator with Dynamic Cascading Technique

Min Jun Li, Si Ce Wang, Bing Bing Yao, Jun Li, Lei Qiu

Photonics & Electromagnetics Research Symposium - Fall (PIERS-Fall)

DOI

2019

A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

Daiguo Xu, Hequan Jiang, Lei Qiu, Xiaoquan Yu, Jianan Wang, Zhengping Zhang, Can Zhu, Shiliu Xu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

邱雷

精选作品

期刊论文

A 16-Bit High-Accuracy R-2R DAC Using Auxiliary-DAC-Assisted Bit-by-Bit Calibration

A 14-b 65.3-dB SNDR 200-MS/s Coarse-fine SAR ADC with Rail-to-Rail Input Common Mode Range in 28-nm CMOS

A 13-b 320-MS/s Noise-Successive-Attenuated SAR ADC with R-C-Traded-Off Reference Buffer

A 150-Msps 77-dB SNDR SAR ADC in 28-nm CMOS

A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS

A 16-Bit 1.6-kS/s ΔΣ Modulator Based on Folded-Cascode Dynamic Amplifier With Speed Enhancement and PVT-Tracking Techniques

A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs

A Reference Assisted Background Calibration Technique With Constant Input Impedance for Time-Interleaved ADCs

A Boundary Mixing Architecture for Two-Channel Frequency-Interleaving Analog-to-Digital Converters

A Output Code Density Histograms Based Calibration Algorithm of Capacitor Mismatch for SAR ADC

A Speed-Enhancement Technique Based on Single-Node-Detection and Bulk-Driven for Inverter-Based Amplifier in Switched-Capacitor Integrator

Capacitor Mismatch Calibration of a 16-Bit SAR ADC Using Optimized Segmentation and Shuffling Scheme

A Low-Power Common-Mode Detector with PVT-Compensation Technique for Dynamic Amplifier in Delta-Sigma Modulator

A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs

A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

A Highly Area-Efficient Switching Scheme based on Charge Sharing and Capacitor Holding for SAR ADCs

A 98.6 dB SNDR SAR ADC With a Mismatch Error Shaping Technique Implemented With Double Sampling

An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

A High-Speed Low-Power Flash ADC with Continued Pipelined Gating in 28-nm CMOS

A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators

A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs

A High-gain High-precision Dynamic Comparator with Dynamic Cascading Technique

A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

研究方向