符玉襄｜上海应用技术大学｜学者主页

2026

Lightweight Multi-View EEG Seizure Detection with a Two-Stage Low-Power BFP FFT–NN Accelerator

C. Ben, Youbin Luo, Zhengling Gu, Kexin Tian, Heng Zhang, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

2026

QSNNA: An Energy-Efficient Quaternary Spiking Neural Network Accelerator for Seizure Detection

Heng Zhang, Linfeng Wu, Linxiang Wang, Youbin Luo, Hao-Chuan Pan, Xinyu Wang, Guoqiang He, Qinyu Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems

Shize Zhou, Wen-Jie Fan, Si-Yue Li, Yongqi Xue, Shi-Ping Li, Songfeng Deng, Jinlun Ji, Tong Cheng, Xin-Yu Wang, Li Li, Yu-Xiang Fu

Integr.

DOI

2026

PIM-NoC: A NoC Architecture with In-Router Processing-in-Memory for DNN Acceleration

Yi Liu, Hai-Xian Ren, Li-Xia Han, Cuiyu Qi, Hui Chen, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2026

HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering

Ziang Wei, Zirui Xu, Sufeng Guo, Chuanchao Gao, Yiyang Gao, Arvind Easwaran, Yu-Xiang Fu

2026

A High-Performance and Low-Resource Reconfigurable Hardware Implementation for Softmax in Transformer

Bangzheng He, Bang-Xin Qin, Han Wang, Chenyang Dai, Lin Yang, Li Li, Yu-Xiang Fu

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

High-Precision Low-Complexity Method and Architecture for Computing Sigmoid and Tanh Functions

Yi Liu, Hai-Xian Ren, Hui Chen, Yu-Xiang Fu, Pin Li, Gang Wu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2026

Fast Modular Reduction Algorithm and Reconfigurable Domain-Specific Architecture Design Based on Generalized Mersenne Primes

Xin-Yu Wang, Guoqiang He, Yilin Wang, Jun Qian, Congyi Sun, Kai Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

A 1.1 μJ/Inference Binary Spiking Neural Network Accelerator for DVS Gesture Recognition

Congyi Sun, Xuseng Zeng, Qiang Tao, Heng Zhang, Qinyu Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2026

Perception-Core: Reconfigurable Energy-Efficient Domain-Specific Architecture with Multimodal Fusion for AIoT

Xin-Yu Wang, Yu-Long Li, Y. Xiang, Yuanhua Deng, Hai-Xian Ren, Hui Chen, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2026

FRRAP: A Fast-Response Reconfigurable AI Processor and Its Application in Four-Class Seizure Monitoring

Heng Zhang, Qiang Tao, C. Ben, Youbin Luo, Guoqiang He, Si-Rui Zhu, Jing-Yi Ma, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2026

Thermal-Aware 3D-IC Floorplan Based On TSV-Coordination Simulated Annealing

Xing-Jie Zou, Wenbo Zhang, Linfeng Wu, Heng Zhang, Xin-Yu Wang, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2026

HTR-Accel: An Energy-Efficient AI Accelerator With Hierarchical Temporal Reuse for Streaming Time-Series Signal Classification

Heng Zhang, Zheng-Lin Gu, Jing-Yi Ma, Yi-Nuo Fu, Cheng-Zhi Wang, Hao-Chuan Pan, Xing-Jie Zou, Hui Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2025

Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip

Tong Cheng, Zi-Rui Xu, Xin-Yi Li, Li Li, Yu-Xiang Fu

Asia and South Pacific Design Automation Conference

DOI

2025

A 5.9 μJ/Inference Reconfigurable Accelerator for Hybrid SNN-ANN Architectures in Event-based Image Recognition

Congyi Sun, Boqi Jia, Qinyu Chen, Wen-Qing Song, Jun Qian, Yu-Xiang Fu, Li Li

Biomedical Circuits and Systems Conference

DOI

2025

NMIX: NoC-Aware Mixed Precision Quantization for Energy-Efficient ML Accelerator

Xin-Yi Li, Eunbin Park, Myeong-Yurl Lee, Wen-Jie Fan, Yu-Xiang Fu, Li Li, Youngjoo Lee

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2025

HengNet: An Ultra-lightweight Model with Two-level Reuse Algorithm for Seizure Detection and Prediction

Heng Zhang, Linxiang Wang, Wen-Jie Fan, Zhengling Gu, Youbin Luo, Xing-Jie Zou, Chang Gao, Qinyu Chen, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2025

MULiN: A NoC-DNN Accelerator Based on In-Network Multiplication

Yi Liu, Cuiyu Qi, Hui Chen, Kai Chen, Yu-Xiang Fu, Li Li

2025 International Symposium of Electronics Design Automation (ISEDA)

DOI

2025

Optimizing Mixed-Precision DNN Scheduling on Heterogeneous SoCs for Enhanced Robustness and Efficiency

Yulong Song, Qiang Tao, Jinlun Ji, Congyi Sun, Yu-Xiang Fu, Li Li

International Conference on Artificial Intelligence Circuits and Systems

DOI

2025

NAME: NoC-based Accelerators Mapping Exploration for High Performance DNN Inference

Jinlun Ji, Hengyue Gao, Heng Zhang, Yuqing Lu, Kaicheng He, Yulong Song, Wen-Jie Fan, Li Li, Yu-Xiang Fu

International Symposium on Circuits and Systems

DOI

2025

FAS-NoC: A Real-Time Fused Approximation Scheme Coordinating Communication and Computation for NoC-Based NN Accelerators

Si-Yue Li, Chuanzhu Liu, Wen-Jie Fan, Heng Zhang, Chenyang Dai, Congyi Sun, Xin-Yu Wang, Li Li, Yu-Xiang Fu

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2025

Efficient Quantization and Data Access for Accelerating Homomorphic Encrypted CNNs

Kai Chen, Xin-Yu Wang, Yu-Xiang Fu, Li Li

Electronics

DOI

2025

LT-OAQ: Learnable Threshold Based Outlier-Aware Quantization and its Energy-Efficient Accelerator for Low-Precision On-Chip Training

Qinkai Xu, Yijin Liu, Yuan Meng, Yang Chen, Yunlong Mao, Li Li, Yu-Xiang Fu

Design, Automation and Test in Europe

DOI

2025

LPABMs: Low-Power Approximate Booth Multipliers designed for CNN accelerators

Chenyang Dai, Yu-Hao Xie, Yu-Xiang Fu, Han Wang, Bangzheng He

International Conference on Field-Programmable Technology

DOI

2025

FPGA-Par: An Efficient Algorithm for Elegant Partitioning in Multi-FPGA Systems

Hengyue Gao, Chenyang Dai, Jinlun Ji, Bin Yan, Qiyue Zhao, Jiangtao Yuan, Feng Li, Li Li, Yu-Xiang Fu

International Symposium on Circuits and Systems

DOI

2025

VETA-DiT: Variance-Equalized and Temporally Adaptive Quantization for Efficient 4-bit Diffusion Transformers

Qinkai Xu, Yi-Jin Liu, Yang Chen, Lin F. Yang, Er-Ran L. Li, Yu-Xiang Fu

Neural Information Processing Systems

DOI

2025

An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes

Congyi Sun, Wenqing Song, Qinyu Chen, Chenyang Dai, Yu-Xiang Fu, Li Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2024

Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators

Wen-Jie Fan, Si-Yue Li, Lingxiao Zhu, Zhonghai Lu, Li Li, Yu-Xiang Fu

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2024

TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator

Xin-Yi Li, Wen-Jie Fan, Heng Zhang, Jinlun Ji, Tong Cheng, Shi-Ping Li, Li Li, Yu-Xiang Fu

ACM Great Lakes Symposium on VLSI

DOI

2024

A General Methodology and Reconfigurable Architecture for Calculating AB-Like Functions in the Complex Field

Ruiqi Wu, Xinyu Wang, Jie Li, Lili Cao, Guoqiang He, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2024

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data

Wenqing Song, Sirui Shen, Cong-Wei Xu, Yilin Wang, Xinyu Wang, Yu-Xiang Fu, Li Li, Zhonghai Lu

IEEE Access

DOI

2024

Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning

Yongqi Xue, Jinlun Ji, Xinming Yu, Shize Zhou, Si-Yue Li, Xin-Yi Li, Tong Cheng, Shi-Ping Li, Kai Chen, Zhonghai Lu, Li Li, Yu-Xiang Fu

IEEE transactions on computers

DOI

2024

HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators

Si-Yue Li, Shize Zhou, Yongqi Xue, Wen-Jie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li, Yu-Xiang Fu

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2024

Four-class EEG Classification for Seizure Prediction and Detection Using a Lightweight CNN-LSTM

Heng Zhang, Dan Wang, Jinlun Ji, Xiaohan Xue, Congyi Sun, Xin-Yu Wang, Qinyu Chen, Yu-Xiang Fu, Li Li

Biomedical Circuits and Systems Conference

DOI

2023

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing

Yu-Xiang Fu, Kai Chen, Wenqing Song, Guoqiang He, Sirui Shen, Huizheng Wang, Chuan Zhang, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2023

Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation

Wan Hong, Hui Chen, Lianghua Quan, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2023

A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow

Lingxiao Zhu, Wen-Jie Fan, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li, Yu-Xiang Fu

IEEE design & test

DOI

2022

Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers

Ruiqi Wu, Hui Chen, Guoqiang He, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2022

A Nearest-Neighbor-Based Thermal Sensor Allocation and Temperature Reconstruction Method for 3-D NoC-Based Multicore Systems

Meng-Hao Guo, Tong Cheng, Xinyi Li, Li Li, Yu-Xiang Fu

IEEE Sensors Journal

DOI

2022

Huicore: A Generalized Hardware Accelerator for Complicated Functions

Hui Chen, Zong-Guang Yu, Jin Xu, Lin Jiang, Zhong-Hai Lu, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2022

Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems

Shize Zhou, Yongqi Xue, Si-Yue Li, Jinlun Ji, Tong Cheng, Li Li, Yu-Xiang Fu

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

DOI

2022

Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks

Congyi Sun, Qinyu Chen, Kai Chen, Guoqiang He, Yu-Xiang Fu, Li Li

International Symposium on Circuits and Systems

DOI

2022

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning

Congyi Sun, Haohan Sun, Jin Xu, Jianing Han, Xin-Yu Wang, Xin-Yu Wang, Qinyu Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2022

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography

Sirui Shen, Wenqing Song, Xinyu Wang, Xin-Yu Shao, Yu-Xiang Fu, Zhong-Hai Lu, Li Li

International Symposium on Circuits and Systems

DOI

2022

Deep Spiking Neural Network with Ternary Spikes

Congyi Sun, Qinyu Chen, Yu-Xiang Fu, Li Li

Biomedical Circuits and Systems Conference

DOI

2022

AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks

Yongqi Xue, Jinlun Ji, Xinyi Li, Siyue Li, Shize Zhou, Tong Cheng, Li Li, Yu-Xiang Fu

ICCD

DOI

2022

Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks

Qinyu Chen, Chang Gao, Yu-Xiang Fu

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2021

Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs

Yu-Xiang Fu, Chuan Zhang, Wenqing Song, Qinyu Chen, Hui Chen, Minghao Zhou, Li Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2021

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT

Heping Yang, Hui Chen, Yu-Xiang Fu, Li Li

International SoC Design Conference

DOI

2021

Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN

Menghao Guo, Tong Cheng, Li Li, Yu-Xiang Fu

International SoC Design Conference

DOI

2021

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers

Hui Chen, Zong-Guang Yu, Yonggang Zhang, Zhong-Hai Lu, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2021

2β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance

Yonggang Zhang, Hui Chen, Yu-Xiang Fu, Li Li

International SoC Design Conference

DOI

2021

A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation

Qinyu Chen, Guoqiang He, Xinyuan Wang, Jin Xu, Sirui Shen, Hui Chen, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2021

LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System

Tong Cheng, Haoyu Du, Li Li, Yu-Xiang Fu

International SoC Design Conference

DOI

2021

Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes

Wenqing Song, Yifei Shen, Yu-Xiang Fu, Chuan Zhang, Li Li

International Symposium on Circuits and Systems

DOI

2021

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation

Hui Chen, Ruiqi Wu, Zhong-Hai Lu, Yu-Xiang Fu, Li Li, Zong-Guang Yu

International Symposium on Circuits and Systems

DOI

2021

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures

Q. Gao, Wenqing Song, Zhong-Hai Lu, Li Li, Yu-Xiang Fu

International Symposium on Circuits and Systems

DOI

2021

Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions

Hui Chen, Heping Yang, Wenqing Song, Zhong-Hai Lu, Yu-Xiang Fu, Li Li, Zong-Guang Yu

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2021

A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers

Jin Xu, Lin Jiang, Hui Chen, Yu-Xiang Fu, Li Li

International SoC Design Conference

DOI

2020

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation

Hui Chen, Kaifeng Cheng, Zhong-Hai Lu, Yu-Xiang Fu, Li Li

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2020

An Efficient Software List Sphere Decoder for Polar Codes

Hua-Yi Zhou, Yu-Xiang Fu, Zai-Chen Zhang, W. Gross, Xiaohu You, Chuan Zhang

Journal of Signal Processing Systems

DOI

2020

An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective

Qinyu Chen, Yan Huang, Rui Sun, Wenqing Song, Zhong-Hai Lu, Yu-Xiang Fu, Li Li

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2020

An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

Hui Chen, Lin Jiang, Heping Yang, Zhong-Hai Lu, Yu-Xiang Fu, Li Li, Zong-Guang Yu

Electronics

DOI

2020

Hardware Implementation of Random Forest Algorithm Based on Classification and Regression Tree

Ziheng Teng, Lijian Chu, Kai Chen, Guoqiang He, Yu-Xiang Fu, Li Li

2020 IEEE International Conference on Information Technology,Big Data and Artificial Intelligence (ICIBA)

DOI

2020

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions

Hui Chen, Lin Jiang, Yuanyong Luo, Zhong-Hai Lu, Yu-Xiang Fu, Li Li, Zong-Guang Yu

International Symposium on Circuits and Systems

DOI

2019

An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks

Qinyu Chen, Yu-Xiang Fu, Wenqing Song, Kaifeng Cheng, Zhong-Hai Lu, Chuan Zhang, Li Li

Electronics

DOI

2019

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC

Yu-Xiang Fu, Li Li, H. Pan, Kun Wang, F. Feng, Qinyu Chen, Chuan Zhang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2019

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs

Yu-Xiang Fu, Qinyu Chen, Guoqiang He, Kai Chen, Zhong-Hai Lut, Chuan Zhang, Li Li

International Symposium on Circuits and Systems

DOI

2019

Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems

Xiangyu Deng, Jin Sha, Xiao-Tian Zhou, Yu-Xiang Fu, Zai-Chen Zhang, Xiaohu You, Chuan Zhang

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2019

ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes

Wenqing Song, Yu-Xiang Fu, Qinyu Chen, Li Li, Chuan Zhang

International Conference on ASIC

DOI

2019

An Efficient Hardware Accelerator for the MUSIC Algorithm

Hui Chen, Kai Chen, Kaifeng Cheng, Qinyu Chen, Yu-Xiang Fu, Li Li

Electronics

DOI

2019

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning

Qinyu Chen, Yu-Xiang Fu, Kaifeng Cheng, Wenqing Song, Zhong-Hai Lu, Li Li, Chuan Zhang

International Symposium on Circuits and Systems

DOI

2018

Design and Application Space Exploration of a Domain-Specific Accelerator System

F. Feng, Li Li, Kun Wang, Yu-Xiang Fu, Guoqiang He, H. Pan

DOI

2017

Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors

Yu-Xiang Fu, Li Li, Kun Wang, Chuan Zhang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2017

Optimized sorting network for successive cancellation list decoding of polar codes

Kun Wang, Li Li, Feng Han, F. Feng, Jun Lin, Yu-Xiang Fu, Jin Sha

IEICE Electronics Express

DOI

2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors

Yu-Xiang Fu, Li Li, H. Pan, Kun Wang, Feng Han, Jun Lin

International Symposium on Circuits and Systems

DOI

2015

基于卡尔曼滤波的低速伺服系统速度信号估计

符玉襄，孙德新，刘银年

《电机与控制应用》

2015

Exploring stacked main memory architecture for 3D GPGPUs

Yuang Zhang, Li Li, A. Jantsch, Zhong-Hai Lu, Ming-Lun Gao, Yu-Xiang Fu, H. Pan

International Conference on ASIC

DOI

2015

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links

Yu-Xiang Fu, Li Li, Yuang Zhang, H. Pan, Feng Han, Kun Wang

International Conference on ASIC

DOI

2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips

Yuang Zhang, Li Li, Zhong-Hai Lu, A. Jantsch, Yu-Xiang Fu, Ming-Lun Gao

International Symposium on Circuits and Systems

DOI

精选作品

期刊论文

Lightweight Multi-View EEG Seizure Detection with a Two-Stage Low-Power BFP FFT–NN Accelerator

QSNNA: An Energy-Efficient Quaternary Spiking Neural Network Accelerator for Seizure Detection

An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems

PIM-NoC: A NoC Architecture with In-Router Processing-in-Memory for DNN Acceleration

HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering

A High-Performance and Low-Resource Reconfigurable Hardware Implementation for Softmax in Transformer

High-Precision Low-Complexity Method and Architecture for Computing Sigmoid and Tanh Functions

Fast Modular Reduction Algorithm and Reconfigurable Domain-Specific Architecture Design Based on Generalized Mersenne Primes

A 1.1 μJ/Inference Binary Spiking Neural Network Accelerator for DVS Gesture Recognition

Perception-Core: Reconfigurable Energy-Efficient Domain-Specific Architecture with Multimodal Fusion for AIoT

FRRAP: A Fast-Response Reconfigurable AI Processor and Its Application in Four-Class Seizure Monitoring

Thermal-Aware 3D-IC Floorplan Based On TSV-Coordination Simulated Annealing

HTR-Accel: An Energy-Efficient AI Accelerator With Hierarchical Temporal Reuse for Streaming Time-Series Signal Classification

Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip

A 5.9 μJ/Inference Reconfigurable Accelerator for Hybrid SNN-ANN Architectures in Event-based Image Recognition

NMIX: NoC-Aware Mixed Precision Quantization for Energy-Efficient ML Accelerator

HengNet: An Ultra-lightweight Model with Two-level Reuse Algorithm for Seizure Detection and Prediction

MULiN: A NoC-DNN Accelerator Based on In-Network Multiplication

Optimizing Mixed-Precision DNN Scheduling on Heterogeneous SoCs for Enhanced Robustness and Efficiency

NAME: NoC-based Accelerators Mapping Exploration for High Performance DNN Inference

FAS-NoC: A Real-Time Fused Approximation Scheme Coordinating Communication and Computation for NoC-Based NN Accelerators

Efficient Quantization and Data Access for Accelerating Homomorphic Encrypted CNNs

LT-OAQ: Learnable Threshold Based Outlier-Aware Quantization and its Energy-Efficient Accelerator for Low-Precision On-Chip Training

LPABMs: Low-Power Approximate Booth Multipliers designed for CNN accelerators

FPGA-Par: An Efficient Algorithm for Elegant Partitioning in Multi-FPGA Systems

VETA-DiT: Variance-Equalized and Temporally Adaptive Quantization for Efficient 4-bit Diffusion Transformers

An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes

Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators

TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator

A General Methodology and Reconfigurable Architecture for Calculating AB-Like Functions in the Complex Field

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data

Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning

HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators

Four-class EEG Classification for Seizure Prediction and Detection Using a Lightweight CNN-LSTM

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing

Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation

A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow

Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers

A Nearest-Neighbor-Based Thermal Sensor Allocation and Temperature Reconstruction Method for 3-D NoC-Based Multicore Systems

Huicore: A Generalized Hardware Accelerator for Complicated Functions

Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems

Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography

Deep Spiking Neural Network with Ternary Spikes

AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks

Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks

Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT

Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers

2β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance

A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation

LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System

Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures

Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions

A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation

An Efficient Software List Sphere Decoder for Polar Codes

An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective

An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

Hardware Implementation of Random Forest Algorithm Based on Classification and Regression Tree

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions

An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs

Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems

ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes

An Efficient Hardware Accelerator for the MUSIC Algorithm

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning

Design and Application Space Exploration of a Domain-Specific Accelerator System

Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors

Optimized sorting network for successive cancellation list decoding of polar codes

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors

基于卡尔曼滤波的低速伺服系统速度信号估计

Exploring stacked main memory architecture for 3D GPGPUs