朱可人｜复旦大学｜学者主页

2026

VSTherm: A Virtual Path-Based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation

Yuan Meng, Zhixuan Dong, Yuyan Wang, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

A Behavior-Centric Methodology for High-Performance Amplifier Sizing

Haochang Zhi, Jintao Li, Keren Zhu, Yun Li, Weiwei Shan, Wanyuan Qu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

AnalogGym-Opt: An LLM-Oriented Optimization Infrastructure for Analog Circuit Sizing with GRPO

Jintao Li, Haochang Zhi, Yongji Long, Weixuan Liu, Yanhan Zeng, Keren Zhu, Shui Yu, Yun Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

ULTRA-2.5D: An Analytical Placement Framework for Ultra-Large-Scale Multi-Reticle Chiplet Systems

Jinhong Huang, Yuyan Wang, Boxiang Song, Chengkai Zhu, Yuman Zeng, Jiayao Li, Keren Zhu, Lang Feng, Changhao Yan, Chixiao Chen, Xuan Zeng

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking

Benchao Zhu, Jiawei Li, Yang Liu, Jianli Chen, Keren Zhu

ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI

2026

HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement

Guanhua Chen, Yujie Yan, J Z Liu, Zecheng Xu, Linxi Qiu, Yumao Wu, Zi Wang, Changhao Yan, Zhaori Bi, Keren Zhu

IEEE International Symposium on Circuits and Systems proceedings

DOI

2026

RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively Parallel Global Routing

Chuyu Wang, Zecheng Xu, Boxiang Song, Zhiang Wang, Fan Yang, Keren Zhu, Xuan Zeng

IEEE International Symposium on Circuits and Systems proceedings

DOI

2026

Submodular Maximization-inspired Adaptive Routing Bend Space Planning

Siting Liu, Peng Xu, Peiyu Liao, Keren Zhu, Yibo Lin, Bei Yu

DOI

2026

PAPlace: Performance-Driven Differentiable Analog Placement

Peng Xu, Yuan Pu, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu

ACM Transactions on Design Automation of Electronic Systems

DOI

2025

DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization

Chuyu Wang, Xinglong Yan, Zecheng Xu, Ke Hu, Keren Zhu, Shuo Li, Fan Yang, Xuan Zeng

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

Ruiyu Lyu, Yuan Meng, Zhaori Bi, Keren Zhu, Changhao Yan, Fan Yang, Xuan Zeng

International Symposium of Electronics Design Automation (ISEDA)

DOI

2025

PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation

Peng Xu, Jindong Tu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

An Iterative FEM Solver for IC Electromagnetic Analysis via Hybrid Geometric-Algebraic Partitioning and Neural Network Optimization

Mingtao Li, Changhao Yan, Tao Cui, Liguo Jiang, Wenliang Dai, Zhaori Bi, Keren Zhu, Xuan Zeng

IEEE Transactions on Microwave Theory and Techniques

DOI

2025

Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization

Jintao Li, Haochang Zhi, Jiang Xiao, Keren Zhu, Yun Li

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing

Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, Xuan Zeng

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement

Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu, Xuan Zeng

DOI

2025

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu, Xuan Zeng

DOI

2025

LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits

Zhou Hongjian, Keren Zhu, Jiaqi Gu

International Symposium on Physical Design

DOI

2025

HeLO: A He terogeneous L ogic O ptimization Framework by Hierarchical Clustering and Graph Learning

Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu

International Symposium on Physical Design

DOI

2025

HOLMES-HLS: Holistic Optimization and Learning-based Multi-model Exploration System for High-level Synthesis

Yu-Jie Yan, Guan-Hua Chen, Ruiyu Lyu, Huizhen Kuang, Kaiwen Zhou, Hao Chen, Ling-Li Wang, Keren Zhu

International Conference on Field-Programmable Technology

DOI

2024

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis

Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng

DOI

2024

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu

DOI

2024

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis

Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng

DOI

2024

ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

Hyunsu Chae, Keren Zhu, B. Mutnury, Doug Wallace, Douglas Winterberg, D. de Araujo, J. Reddy, Adam R. Klivans, David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2024

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation

Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan

arXiv.org

DOI

2024

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning

Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zi-Xuan Jiang, D. de Araujo, Doug Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan

Asia and South Pacific Design Automation Conference

DOI

2024

A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing

Souradip Poddar, A. Budak, Lin-Ran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yao-Yao Jia, David Z. Pan

Design, Automation and Test in Europe

DOI

2024

Universal Process Migration Solution of MAGICAL for Analog IC Layout Automation

Yu-Feng Wei, Yi-Fan Xu, Keren Zhu, Ye Lu

China Semiconductor Technology International Conference

DOI

2023

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2023

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2023

Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities

A. Budak, Keren Zhu, Hao Chen, Souradip Poddar, Lin-Ran Zhao, Yaoyao Jia, David Z. Pan

ACM International Symposium on Physical Design

DOI

2023

Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks

A. Budak, Keren Zhu, David Z. Pan

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

DOI

2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits

Hao Chen, K. Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren

ACM International Symposium on Physical Design

DOI

2022

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper)

Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan

Asia and South Pacific Design Automation Conference

DOI

2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, G. Kokai, Brian Zimmer, C. T. Gray, Brucek Khailany, David Z. Pan, Haoxing Ren

ACM International Symposium on Physical Design

DOI

2022

TAG: Learning Circuit Spatial Embedding From Layouts

Keren Zhu, Hao Chen, Walker J. Turner, G. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

DOI

2022

1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation

Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan

IEEE Solid-State Circuits Letters

DOI

2022

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper)

A. Budak, Zi-Xuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan

Asia and South Pacific Design Automation Conference

DOI

2022

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan

Asia and South Pacific Design Automation Conference

DOI

2021

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

Design Automation Conference

DOI

2021

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler

Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

DOI

2021

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC

Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan

IEEE Custom Integrated Circuits Conference

DOI

2020

Challenges and opportunities toward fully automated analog layout design

Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, David Z. Pan

Journal of Semiconductors

DOI

2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan

Design, Automation and Test in Europe

DOI

2020

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

DOI

2020

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Mingjie Liu, Wu-Xi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan

Asia and South Pacific Design Automation Conference

DOI

2020

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network

Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan

Workshop on Machine Learning for CAD

DOI

2020

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

DOI

2020

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII

Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan

IEEE design & test

DOI

2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan

Design Automation Conference

DOI

2019

ML-based Routing Guidance Generation Data Pre-processing Trained ML Model Guided AMS Routing Guided Detailed Routing Post-processing ML Model Training AMS Circuit Layout Database Dashed : Training Solid : Inference Fr am ew or k Placement Routed Layout

Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

精选作品

期刊论文

VSTherm: A Virtual Path-Based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation

A Behavior-Centric Methodology for High-Performance Amplifier Sizing

AnalogGym-Opt: An LLM-Oriented Optimization Infrastructure for Analog Circuit Sizing with GRPO

ULTRA-2.5D: An Analytical Placement Framework for Ultra-Large-Scale Multi-Reticle Chiplet Systems

A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking

HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement

RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively Parallel Global Routing

Submodular Maximization-inspired Adaptive Routing Bend Space Planning

PAPlace: Performance-Driven Differentiable Analog Placement

DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization

Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation

An Iterative FEM Solver for IC Electromagnetic Analysis via Hybrid Geometric-Algebraic Partitioning and Neural Network Optimization

Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization

MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits

HeLO: A He terogeneous L ogic O ptimization Framework by Hierarchical Clustering and Graph Learning

HOLMES-HLS: Holistic Optimization and Learning-based Multi-model Exploration System for High-level Synthesis

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis

ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning

A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing

Universal Process Migration Solution of MAGICAL for Analog IC Layout Automation

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System

Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities

Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks

Reinforcement Learning Guided Detailed Routing for Custom Circuits

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

TAG: Learning Circuit Spatial Embedding From Layouts

1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper)

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC

Challenges and opportunities toward fully automated analog layout design

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

ML-based Routing Guidance Generation Data Pre-processing Trained ML Model Guided AMS Routing Guided Detailed Routing Post-processing ML Model Training AMS Circuit Layout Database Dashed : Training Solid : Inference Fr am ew or k Placement Routed Layout

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

预印本

When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDA

Differentiable Partitioning With Dual-Max 3D Wirelength Model and Hybrid Bonding Terminal Awareness for Optimized 3D Placement

Safe Hypergraph Contraction via Capacity-Aware Repair Certificates

研究方向