张奥扬｜清华大学｜学者主页

2026

HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling

Sijia Lu, Wenping Zhu, Bohan Yang, Jiajun Yang, Tongwei Dai, Chen Chen, Xiangdong Han, Jinjiang Yang, Hanning Wang, Min Zhu, Shaojun Wei, Aoyang Zhang, Leibo Liu

IEEE Journal of Solid-State Circuits

DOI

2026

SiWB: A 28-nm 800-MHz 4.2-to-14.2-Gb/s/W Configurable Multi-Core Architecture for White-Box Block Cipher With Area-Efficient Random Linear Transformation and Load-Aware Inter-Core Scheduling

Xiangren Chen, Bohan Yang, Wenping Zhu, Hanning Wang, Jinjiang Yang, Min Zhu, Aoyang Zhang, Leibo Liu

IEEE Journal of Solid-State Circuits

DOI

2026

HiPACS: A Mixed-Signal In-Memory Complete SAT Solver with Hierarchical Architecture and Parallel Boolean Constraint Propagation

Iris Ying Chou, Yi Cheng Huang, Hao Kong, Jingheng Ma, Yuqi Liu, Liangwei Li, Xiao Li, Meng Han, Jianfeng Zhu, Hanning Wang, Shaojun Wei, Aoyang Zhang, Leibo Liu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

A 28-nm, 8.3-mm 2 , 76.9- μ J/Pairing Compiler-Driven Crypto-Processor for Hybrid ZKP–PBC Application With Software–Hardware Co-Design

Xiangren Chen, Bohan Yang, Jinfan Zhang, Yifan Jiang, Wenping Zhu, Hanning Wang, Min Zhu, Aoyang Zhang, Leibo Liu

IEEE Journal of Solid-State Circuits

DOI

2026

HawkPU: An Efficient and Low-Latency Hardware Architecture for HAWK Signature Generation and Verification

Rui Wang, Yihong Zhu, Wenping Zhu, Yi Ouyang, Bohan Yang, Hanning Wang, Min Zhu, Chen Chen, Aoyang Zhang, Leibo Liu

IACR Transactions on Cryptographic Hardware and Embedded Systems

DOI

2026

An H-Band CMOS Frequency Doubler with 6.01dBm Single-Element P out and 1.49%-DC-to-RF-Efficiency Using Dual-Harmonic Continuous-Mode Tuning Technique

Weiping Wu, Yanjun Ma, Xun Bao, Lei Zhang, Aoyang Zhang

IEEE Custom Integrated Circuits Conference (CICC)

DOI

2026

25.6 A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking

Cankun Zhao, Hanyue Shui, Bohan Yang, Wenping Zhu, Yuluan Cao, Hou Zhang, Yuqi Liu, Xiangdong Han, Shuying Yin, Weinan Chen, Hanning Wang, Jie Yang, Min Zhu, Aoyang Zhang, Leibo Liu

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI

2026

An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors

Xinyi Wu, Chenxu Zhao, Hui Chen, Xun Bao, Yaolong Hu, Aoyang Zhang, Leibo Liu

IEEE Solid-State Circuits Letters

DOI

2026

RedPanda: A Unified Compilation Framework for Dataflow-Based CGRAs and High-Level Synthesis

Yi Huang, Xiangyu Kong, Jianfeng Zhu, Mingyu Gao, Shaojun Wei, Aoyang Zhang, Leibo Liu

IEEE Transactions on Parallel and Distributed Systems

DOI

2026

A 5GS/s Staggered Working Point Ensemble TRNG with a Stochastic Model Achieving 4064.5 Mbps Entropy-Throughput and 997.6 fJ/Entropy-Bit

Shaonan Wu, Ziheng Ma, Bohan Yang, Yuanxiao Wang, Zhiqi Yang, Weinan Chen, Hanning Wang, Min Zhu, Aoyang Zhang, Leibo Liu

DOI

2026

SharpSAT: A Heuristic-Learning-Based SAT Accelerator Achieving 0.8μs/16.1μs Solution Time in SAT/UNSAT Cases

Yi Huang, Hao Kong, Iris Ying Chou, Bin Wang, Xiang-Yu Kong, Jian-Feng Zhu, Liangwei Li, Xiao Li, Han-Ning Wang, Aoyang Zhang, Lei-Bo Liu

IEEE International Solid-State Circuits Conference

DOI

2025

基于NTT/INTT优化的LAC格密码高速专用硬件实现

朱益宏，王汉宁，朱文平，韩栋钧，罗一杰，张奥扬，刘雷波

《微电子学与计算机》

DOI

2025

EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform

Yi Huang, Xin Gong, Xiangyu Kong, Dibei Chen, Jianfeng Zhu, Wenping Zhu, Liangwei Li, Mingyu Gao, Shaojun Wei, Aoyang Zhang, Leibo Liu

Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings

DOI

2025

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and −30.8dB EVM in 65nm CMOS

Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo‐Wei Chen

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI

2025

A Monolithic Reconfigurable RRAM CIM Array Integrating PUF, TRNG, and a Lightweight Block Cipher for Secure Edge AI

Songqi Wang, Shuang Liang, Shaonan Wu, Zhiqi Yang, Jichang Yang, Xinyuan Zhang, Yi Li, Yuhao Zhang, Zi Wang, Aoyang Zhang, Han Wang

Technical digest - International Electron Devices Meeting/Technical digest

DOI

2025

A 200Mb/s 273fJ/b metastability-based TRNG without Postprocessing Using Body Biasing Tuning with On-chip Faraday Cage Shielding in 65nm CMOS

Aoyang Zhang, Shaonan Wu, Bohan Yang, Yuanxiao Wang, Zhiqi Yang, Tianxia Zhao, Wenping Zhu, Hanning Wang, Min Zhu, Leibo Liu

IEEE Asian Solid-State Circuits Conference (A-SSCC)

DOI

2025

Chameleon-SAT: An Adaptive Boolean Satisfiability Accelerator Using Mixed-Signal In-Memory Computing for Versatile SAT Problems

Iris Ying Chou, Hao Kong, Yi Huang, Jianfeng Zhu, Wenping Zhu, Shaojun Wei, Aoyang Zhang, Leibo Liu

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory

Weiyi Sun, Mingyu Gao, Zhaoshi Li, Aoyang Zhang, Iris Ying Chou, Jianfeng Zhu, Shaojun Wei, Leibo Liu

Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings

DOI

2025

A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA

Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, M. Chen

IEEE Journal of Solid-State Circuits

DOI

2025

PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems

Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Qi Zhao, Min Zhu, Jinjiang Yang, Chen Chen, Qichao Tao, Han-Ning Wang, Guang Yang, Shao-Jun Wei, Aoyang Zhang, Lei-Bo Liu

IEEE Journal of Solid-State Circuits

DOI

2025

17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing

Sijia Lu, Wenping Zhu, Bo-Han Yang, Jia-Jun Yang, Tongwei Dai, Chen Chen, Xiangdong Han, Jinjiang Yang, Han-Ning Wang, Min Zhu, Shao-Jun Wei, Aoyang Zhang, Lei-Bo Liu

IEEE International Solid-State Circuits Conference

DOI

2024

16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems

Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Min Zhu, Qi Zhao, Jinjiang Yang, Chen Chen, Qichao Tao, Guang Yang, Aoyang Zhang, Shaojun Wei, Lei-Bo Liu

IEEE International Solid-State Circuits Conference

DOI

张奥扬

精选作品

期刊论文

HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling

SiWB: A 28-nm 800-MHz 4.2-to-14.2-Gb/s/W Configurable Multi-Core Architecture for White-Box Block Cipher With Area-Efficient Random Linear Transformation and Load-Aware Inter-Core Scheduling

HiPACS: A Mixed-Signal In-Memory Complete SAT Solver with Hierarchical Architecture and Parallel Boolean Constraint Propagation

A 28-nm, 8.3-mm 2 , 76.9- μ J/Pairing Compiler-Driven Crypto-Processor for Hybrid ZKP–PBC Application With Software–Hardware Co-Design

HawkPU: An Efficient and Low-Latency Hardware Architecture for HAWK Signature Generation and Verification

An H-Band CMOS Frequency Doubler with 6.01dBm Single-Element P out and 1.49%-DC-to-RF-Efficiency Using Dual-Harmonic Continuous-Mode Tuning Technique

25.6 A 17%/27% Area-/Energy-Overhead Glitch-Transition Secure SHA-3 Engine Fusing Dual-Rail Precharge Logic and Asymmetric Masking

An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors

RedPanda: A Unified Compilation Framework for Dataflow-Based CGRAs and High-Level Synthesis

A 5GS/s Staggered Working Point Ensemble TRNG with a Stochastic Model Achieving 4064.5 Mbps Entropy-Throughput and 997.6 fJ/Entropy-Bit

SharpSAT: A Heuristic-Learning-Based SAT Accelerator Achieving 0.8μs/16.1μs Solution Time in SAT/UNSAT Cases

基于NTT/INTT优化的LAC格密码高速专用硬件实现

EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and −30.8dB EVM in 65nm CMOS

A Monolithic Reconfigurable RRAM CIM Array Integrating PUF, TRNG, and a Lightweight Block Cipher for Secure Edge AI

A 200Mb/s 273fJ/b metastability-based TRNG without Postprocessing Using Body Biasing Tuning with On-chip Faraday Cage Shielding in 65nm CMOS

Chameleon-SAT: An Adaptive Boolean Satisfiability Accelerator Using Mixed-Signal In-Memory Computing for Versatile SAT Problems

Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory

A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA

PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems

17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing

16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems

会议论文

Impact of Process Variations and Defects on RF Front-end in Nanoscale CMOS

研究方向