马昱春

2022

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow

ACM Transactions on Reconfigurable Technology and Systems

DOI

2018

Lattice-Based Scheduling for Multi-FPGA Systems

International Conference on Field-Programmable Technology

DOI

2017

基于MPSoC并行调度的矩阵乘法加速算法研究

《计算机科学》

2016

基于混合式两阶段的动态部分重构FPGA软硬件划分算法

《清华大学学报(自然科学版)》

DOI

2016

Relation-oriented resource allocation for multi-accelerator systems

IEEE International Conference on Application-Specific Systems, Architectures, and Processors

DOI

2016

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

IEEE International Conference on Application-Specific Systems, Architectures, and Processors

DOI

2016

Modular placement for interposer based multi-FPGA systems

ACM Great Lakes Symposium on VLSI

DOI

2015

HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric

International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)

DOI

2014

HS3-DPG: Hierarchical Simulation for 3-D P/G Network

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2014

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs

Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design

DOI

2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes

ACM Journal on Emerging Technologies in Computing Systems

DOI

2014

Efficient region-aware P/G TSV planning for 3D ICs

DOI

2014

An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

Advances in intelligent systems research/Advances in Intelligent Systems Research

DOI

2013

一种时间复杂度为O(m)的无向超图核值求解算法

《小型微型计算机系统》

2013

基于结点匹配策略的赋权超图核值实验比较

《计算机工程》

2013

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

Journal of Computer Science and Technology

DOI

2013

基于运行时基本代码块的可重构软硬件协同设计

《清华大学学报(自然科学版)》

DOI

2013

Whitespace-aware TSV arrangement in 3D clock tree synthesis

IEEE Computer Society Annual Symposium on VLSI

DOI

2013

RALP: Reconvergence-aware layer partitioning for 3D FPGAs

International Conference on ReConFigurable Computing and FPGAs (ReConFig)

DOI

2013

Power-driven NoC design optimization with low swing interconnect

International Conference on Communications, Circuits and Systems

DOI

2013

Defect-tolerant routing algorithm for low power NoCs based on buffer-shared router architecture

International Conference on Communications, Circuits and Systems

DOI

2013

Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs

IEEE International Conference on ASIC (ASICON)

DOI

2013

Incremental 3D NoC synthesis based on physical-aware router merging algorithm

IEEE International Conference on ASIC (ASICON)

DOI

2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

IET Circuits Devices & Systems

DOI

2013

Efficient custom instruction generation based on characterizing of basic blocks

IEEE International Conference on Computer Supported Cooperative Work in Design (CSCWD)

DOI

2013

Automatic enhanced CDFG generation based on runtime instrumentation

IEEE International Conference on Computer Supported Cooperative Work in Design (CSCWD)

DOI

2013

UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS

Journal of Circuits Systems and Computers

DOI

2013

TSV-aware topology generation for 3D Clock Tree Synthesis

International Symposium on Quality Electronic Design (ISQED)

DOI

2013

HS3DPG: Hierarchical simulation for 3D P/G network

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2012

超图划分问题的元胞自动机模型及算法研究

《计算机工程》

2012

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs

Integration

DOI

2012

ISBA

DOI

2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

IEEE Computer Society Annual Symposium on VLSI

DOI

2012

SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator

DOI

2012

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

DOI

2012

Thermal-aware power network design for IR drop reduction in 3D ICs

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2012

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs

Lecture notes in computer science

DOI

2011

Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2011

Incremental layout optimization for NoC designs based on MILP formulation

IEEE International Conference on ASIC (ASICON)

DOI

2011

Tree-Based Partitioning Approach for Network-on-Chip Synthesis

International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)

DOI

2011

Circuit-level delay modeling considering both TDDB and NBTI

International Symposium on Quality Electronic Design (ISQED)

DOI

2011

Novel and efficient min cut based voltage assignment in gate level

International Symposium on Quality Electronic Design (ISQED)

DOI

2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2011

On-chip hybrid power supply system for wireless sensor nodes

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2011

Network flow-based simultaneous retiming and slack budgeting for low power design

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2011

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2010

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Integration

DOI

2010

THERMAL IMPACTS OF LEAKAGE POWER IN 2D/3D FLOORPLANNING

Journal of Circuits Systems and Computers

DOI

2010

Incremental I/O planning with white space redistribution for flip-chip design

International Conference on Communications, Circuits and Systems

DOI

2010

Simulation and analysis of P/G noise in TSV based 3D MPSoC

DOI

2010

Thermal effects of leakage power in 3D ICs

DOI

2010

Simultaneous slack budgeting and retiming for synchronous circuits optimization

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2010

PS-FPG: Pattern selection based co-design of floorplan and Power/Ground network with wiring resource optimization

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2010

Session details: New techniques in technology mapping

DOI

2009

Congestion-driven floorplanning based on two-stage optimization

IEEE International Conference on ASIC (ASICON)

DOI

2009

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage

ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)

DOI

2009

Simultaneous buffer and interlayer via planning for 3D floorplanning

International Symposium on Quality of Electronic Design (ISQED)

DOI

2009

Incremental power optimization for multiple supply voltage design

International Symposium on Quality of Electronic Design (ISQED)

DOI

2009

A novel thermal optimization flow using incremental floorplanning for 3D ICs

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2009

Hybrid Algorithm for Floorplanning Using B*-tree Representation

DOI

2009

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2009

Modern Floorplanning with Boundary Clustering Constraint

IEEE Computer Society Annual Symposium on VLSI

DOI

2009

Multi-objective Floorplanning Based on Fuzzy Logic

International Conference on Fuzzy Systems and Knowledge Discovery (FSKD)

DOI

2008

Voltage island aware incremental floorplanning algorithm based on MILP formulation

International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

DOI

2008

An efficient thermal optimization flow using incremental floorplanning for 3D microprocessors

International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

DOI

2008

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

ACM Journal on Emerging Technologies in Computing Systems

DOI

2008

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization

International Symposium on Quality Electronic Design (ISQED)

DOI

2007

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2007

Fine grain 3D integration for microarchitecture design through cube packing exploration

Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design

DOI

2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning

IEEE International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)

DOI

2007

Simultaneous Optimization of Performance and Thermal Effects Based on Two-stage Microarchitectural Floorplanning

International Conference on Communications, Circuits and Systems

DOI

2007

A Fast 3D-BSG Algorithm for 3D Packing Problem

IEEE International Symposium on Circuits and Systems proceedings

DOI

2007

An accurate and efficient probabilistic congestion estimation model in x architecture

International Workshop on System Level Interconnect Prediction (SLIP)

DOI

2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement

ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI

2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2007

Interconnect Power Optimization Based on Timing Analysis

IEEE Computer Society Annual Symposium on VLSI

DOI

2006

A Novel Frequency Constrained Floorplanning Algorithm

International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

DOI

2006

Cubic Packing with Various Candidates for 3D IC Design

International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

DOI

2006

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

DOI

2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List

Journal of Computer Science and Technology

DOI

2006

VLSI Block Placement With Alignment Constraints

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

DOI

2006

An automated design flow for 3d microarchitecture evaluation

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2005

基于角模块布图表示的增量式布图规划算法(英文)

Journal of Semiconductors

2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning

International Symposium on Quality of Electronic Design (ISQED)

DOI

2004

芯片级布图规划中的缓冲器规划算法

《中国科学:技术科学》

2004

Stairway compaction using corner block list and its applications with rectilinear blocks

ACM Transactions on Design Automation of Electronic Systems

DOI

2004

Fast evaluation of Bounded Slice-line Grid

Journal of Computer Science and Technology

DOI

2004

Buffer allocation algorithm with consideration of routing congestion

DOI

2003

Arbitrary convex and concave rectilinear block packing based on corner block list

DOI

2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Proceedings - ACM IEEE Design Automation Conference

DOI

2003

An integrated floorplanning with an efficient buffer planning algorithm

International Symposium on Physical Design

DOI

2002

角模块序列布图表示及基于角模块序列表示的边界约束布图规划算法

《中国科学:技术科学》

2002

A compact algorithm for placement design using corner block list representation

DOI

2002

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks

DOI

2001

Floorplan with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List

DOI

2001

Floorplanning with abutment constraints based on corner block list

Integration

DOI

2001

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Proceedings - ACM IEEE Design Automation Conference

DOI

2001

VLSI floorplanning with boundary constraints based on corner block list

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2008

Design Space Exploration for 3D Integrated Circuits

2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings Ⅲ

2000

A Non-Slicing Floorplanning Algorithm Using Corner Block List Topological Representation

Electronic Communication Systems--Proceedings of the 2000 IEEE Asia-Pacific Conference on Circuits and Systems

2009

Thermal-Aware 3D Floorplan

Integrated circuits and systems

DOI

2007

ON HANDLING OF INCREMENTAL FLOORPLANNING FOR 3D ICS

WORLD SCIENTIFIC eBooks

DOI