蔡烁｜长沙理工大学｜学者主页

2026

面向高速读写需求的宇航级抗辐射静态随机存储器加固单元设计

蔡烁，帅威，胡星，梁鑫杰，黄珠，余飞

《电子与信息学报》

2026

宇航环境下基于RHBD的SRAM抗双节点翻转研究综述

帅威，蔡烁，陈俊伊，陈俊哲，梁鑫杰，黄珠，魏懋萱

《集成电路与嵌入式系统》

2026

An Error-Compensated Configurable Approximate Recursive Multiplier for Energy-Efficient Image Processing and CNN Inference

Siyu Wang, Shuo Cai, 黄卉蕾, Wen He, Fei Yu, Jie Jin

Electronics

DOI

2026

Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks

Shuo Cai, Wen He, Huilei Huang, Zhengbang Long

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

A transistor-stacking-based SRAM architecture for power reduction with high speed and high reliability

Shuo Cai, Zhu Huang, Mao-Xuan Wei, Fei Yu

Microelectronics and reliability

DOI

2026

A low-power and leakage 14T SRAM cell with multinode upset tolerance for aerospace applications

Shuo Cai, Zhu Huang, W. Shuai, Fei Yu

Microelectronics Journal

DOI

2026

URDT16T: An Ultrafast Read and Double Node Upset Tolerant SRAM for Space Applications

Shuo Cai, W. Shuai, Jun-Zhe Chen, Xing Hu, Jun Cai, Shuai Chen

International Test Conference in Asia

DOI

2026

High-Performance TNU-Tolerant SRAM Cells via Redundant-Node Hardening for Reliable Applications

Jun-Zhe Chen, Shuo Cai, W. Shuai, Mao-Xuan Wei, Fei Yu

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

Layout-Hardened 18T SRAM With High Reliability and Low Power for Aerospace Applications

Shuo Cai, Jun-Zhe Chen, W. Shuai, Xin-Jie Liang, Jun-Yi Chen, Fei Yu

International Test Conference in Asia

DOI

2026

Replacement-Based Key-Controlled Circuits: A New Lightweight Logic-Locking Technique to Prevent the SAT Attack and Its Variants

Weizheng Wang, Lu Zhao, Shuo Cai

Applied Sciences

DOI

2025

SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF

Weizheng Wang, Zhizhi Wu, Jinhai Chen, Peng Liu, Shuo Cai, Neal N. Xiong

IEEE Internet of Things Journal

DOI

2025

Approximate multiplier design and error estimate model based on partial carry truncation

Shuo Cai, Chao Huang, Fei Yu, Weizheng Wang, Lairong Yin

AEU - International Journal of Electronics and Communications

DOI

2025

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications

Shuo Cai, Xin-Jie Liang, Zhu Huang, Weizheng Wang, Fei Yu

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2024

基于相关性分离的逻辑电路敏感门定位算法

蔡烁，何辉煌，余飞，尹来容，刘洋

《电子与信息学报》

2024

A radiation-hardened 20T SRAM Cell with high reliability and low power consumption

Shuo Cai, Xin-Jie Liang, Yan Wen, Fei Yu, Lairong Yin

International Test Conference in Asia

DOI

2024

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks

Weizheng Wang, Xingxing Gong, Xiangqi Wang, Shuo Cai, Peng Liu, Neal N. Xiong

IEEE Internet of Things Journal

DOI

2024

A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation

Weizheng Wang, Xingxing Gong, Shuo Cai, Jiaming Liu, Xiangqi Wang

IEEE Access

DOI

2023

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs

Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lai-Rong Yin

Integr.

DOI

2023

Low-power and high-speed SRAM cells for double-node-upset recovery

Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu

Integr.

DOI

2023

A highly reliable and low-power cross-coupled 18T SRAM cell

Shuo Cai, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li

Microelectronics Journal

DOI

2023

A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design

Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu

Asian Test Symposium

DOI

2023

A secure scan architecture using parallel latch-based lock

Weizheng Wang, Jian Liang, Xiangqi Wang, Xian-Min Pan, Shuo Cai

Integr.

DOI

2022

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation

Shuo Cai, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu

Journal of electronic testing

DOI

2022

Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm

Shuo Cai, Sicheng Wu, Weizheng Wang, Fei Yu, Lai-Rong Yin

JSTS Journal of Semiconductor Technology and Science

DOI

2022

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture

Weizheng Wang, Xiangqi Wang, Jin Wang, N. Xiong, Shuo Cai, Peng Liu

IEEE Transactions on Systems, Man & Cybernetics. Systems

DOI

2021

FPGA implementation and image encryption application of a new PRNG based on a memristive Hopfield neural network with a special activation gradient

Fei Yu, Zi-Nan Zhang, Hui Shen, Yuanyuan Huang, Shuo Cai, Sichun Du

Chinese Physics B

DOI

2021

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory

Peng Liu, Zhiqiang You, Ji-Gang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yin-He Han

IEEE Transactions on Emerging Topics in Computing

DOI

2021

A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design

Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang

International Test Conference in Asia

DOI

2021

Preventing Scan-Based Side-Channel Attacks by Scan Obfuscating with a Configurable Shift Register

Weizheng Wang, Yin Chen, Shuo Cai, Yan Peng

Security and Communication Networks

DOI

2021

A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself

Weizheng Wang, Yan Peng, Zuo-Ting Ning, Peng Liu, Shuo Cai

JSTS Journal of Semiconductor Technology and Science

DOI

2020

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults

Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lai-Rong Yin, Bo Li

Journal of electronic testing

DOI

2020

An Efficient Degraded Deductive Fault Simulator for Small-Delay Defects

Tie-Qiao Liu, Ting Yu, Shuo Wang, Shuo Cai

IEEE Access

DOI

2019

低延迟低电压电流比较器

余飞，高雷，宋云，蔡烁

《半导体技术》

DOI

2019

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

Shuo Cai, Weizheng Wang, Fei Yu, Binyong He

Journal of electronic testing

DOI

2019

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

Weizheng Wang, Zhuo Deng, Jin Wang, A. Sangaiah, Shuo Cai, Zafer Almakhadmeh, Amr Tolba

Italian National Conference on Sensors

DOI

2019

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks

Weizheng Wang, Jin-Cheng Wang, Wei Wang, Peng Liu, Shuo Cai

IEEE Access

DOI

2018

“新工科”背景下非计算机类专业计算机网络课程教学探索

余飞，蔡烁，李利香，高雷

《计算机时代》

2018

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory

Peng Liu, W. Jigang, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai

Asian Test Symposium

DOI

2017

用KM算法增强测试集的频谱主分量

邝继顺，周颖波，蔡烁，皮霄林

《电子测量与仪器学报》

2017

成果导向的信息类专业电路系列课程改革研究

蔡烁，王威，王新，李骥，朱诗源

《计算机时代》

2017

Reliability evaluation of logic circuits based on transient faults propagation metrics

Shuo Cai, Fei Yu, Weizheng Wang, Tie-Qiao Liu, Peng Liu, Wei Wang

IEICE Electronics Express

DOI

2017

A novel test data compression approach based on bit reversion

Shuo Cai, Yinbo Zhou, Peng Liu, Fei Yu, Wei Wang

IEICE Electronics Express

DOI

2017

Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar

Peng Liu, Zhiqiang You, Jishun Kuang, Michael Elimu, Shuo Cai, Weizheng Wang

DOI

2016

Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

Weizheng Wang, Jin-Cheng Wang, Shuo Cai, Wei Su, Lingyun Xiang

DOI

2015

基于伯努利分布的逻辑电路可靠度计算方法

蔡烁，邝继顺，刘铁桥，凌纯清，尤志强

《电子学报》

2015

一种用于测试数据压缩的自适应EFDR编码方法

邝继顺，周颖波，蔡烁

《电子与信息学报》

2015

基于差错传播概率矩阵的时序电路软错误可靠性评估

蔡烁，邝继顺，张亮，刘铁桥，王伟征

《计算机学报》

2015

逻辑电路软错误可靠性评估方法研究

蔡烁

《湖南大学》

2015

一种用于测试数据压缩的改进型EFDR编码方法

邝继顺，周颖波，蔡烁，皮霄林

《电子测量与仪器学报》

2015

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

Shuo Cai, J. Kuang, Tie-qiao Liu, Weizheng Wang

DOI

2015

An efficient small‐delay faults simulator based on critical path tracing

Tie-Qiao Liu, Jishun Kuang, Shuo Cai, Zhiqiang You

International journal of circuit theory and applications

DOI

2015

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

Weizheng Wang, Shuo Cai, Lingyun Xiang

DOI

2015

Harzard-Based ATPG for Improving Delay Test Quality

Tie-Qiao Liu, Yingbo Zhou, Yi Liu, Shuo Cai

Journal of electronic testing

DOI

2014

考虑信号相关性的逻辑电路可靠度计算方法

蔡烁，邝继顺，刘铁桥，王伟征

《电子学报》

2014

一种将测试集嵌入到Test-per-Clock位流中的方法

Tie-Qiao Liu, Jishun Kuang, Shuo Cai, Zhiqiang You

DOI

2014

An effective logic BIST scheme based on LFSR-reseeding and TVAC

Tie-Qiao Liu, Jishun Kuang, Shuo Cai, Zhiqiang You

DOI

2014

An effective deterministic test generation for test-per-clock testing

Tie-Qiao Liu, Jishun Kuang, Zhiqiang You, Shuo Cai

IEEE Aerospace and Electronic Systems Magazine

DOI

2014

An Efficient Reliability Estimation Method for Gate-level Circuit: An Efficient Reliability Estimation Method for Gate-level Circuit

Shuo Cai, Ji-shun Kuang, Tie-Qiao Liu, Yingbo Zhou

DOI

2014

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Weizheng Wang, Shuo Cai, Lingyun Xiang

DOI

2013

Low power logic BIST with high test effectiveness

Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang

IEICE Electronics Express

DOI

2013

An Efficient Mixed-Mode BIST Scheme for Test-Per-Clock Testing

Tie-Qiao Liu, Jishun Kuang, Shuo Cai, Yinbo Zhou, Zhiqiang You

2012

一种高效的小时延故障模拟方法

周亮，邝继顺，蔡烁

《小型微型计算机系统》

2012

一种基于串行移位的测试数据生成方法

蔡烁，邝继顺，刘铁桥

《计算机科学》

2012

一种多扫描链混合测试数据压缩方法

蔡烁，邝继顺，刘铁桥

《计算机工程》

2012

波形模拟器关于组合电路中竞争冒险的应用

蔡烁，杨致远，刘舜

《微电子学与计算机》

2012

浅谈如何在计算机专业教学中培养创新型人才

蔡烁，王新，陈沅涛

《中国电力教育》

2012

Method to test redundant stuck-at faults considering logic gates' delay

Shuo Cai

2012

New Test Generation Scheme Based on Serial Shifter

Shuo Cai, Jishun Kuang, Tie-Qiao Liu

2011

独立学院计算机科学与技术专业人才培养模式研究

陈沅涛，龙际珍，蔡烁

《中国电力教育》

2011

Embedding N-Detect Test Set into Controlled Bits Stream

Tie-Qiao Liu, Jishun Kuang, Weizheng Wang, Zhiqiang You, Shuo Cai

DOI

2010

基于VHDL的非系统前馈卷积码编码器设计

蔡烁，曹伟，王新

《微计算机信息》

2008

用全速电流测试方法检测PIC12F509微处理器

邓杭剑，邝继顺，蔡烁

《微处理机》

2008

Using at Speed Current Testing Method to Test PIC12F509 Microprocessor

Shuo Cai

2008

Test Pattern Generation Algorithm Based on CUT's Feedback

Shuo Cai

2007

一种检测冗余故障的瞬态电流测试方法

崔昌明，邝继顺，蔡烁

《微电子学与计算机》

2007

时延故障测试产生算法与IDDT测试实验研究

蔡烁

《湖南大学》

2007

一种基于IDDT测试的时延故障测试产生算法

蔡烁，邝继顺，崔昌明

《微处理机》

2007

A Method to Test Redundant Faults Using IDDT Testing

Shuo Cai

A Low-Area Overhead Secure Scan Architecture Resisting Scan-Based Attacks for Crypto Chips

Weizheng Wang, Jin-Cheng Wang, Shuo Cai, Peng Liu

精选作品

期刊论文

面向高速读写需求的宇航级抗辐射静态随机存储器加固单元设计

宇航环境下基于RHBD的SRAM抗双节点翻转研究综述

An Error-Compensated Configurable Approximate Recursive Multiplier for Energy-Efficient Image Processing and CNN Inference

Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks

A transistor-stacking-based SRAM architecture for power reduction with high speed and high reliability

A low-power and leakage 14T SRAM cell with multinode upset tolerance for aerospace applications

URDT16T: An Ultrafast Read and Double Node Upset Tolerant SRAM for Space Applications

High-Performance TNU-Tolerant SRAM Cells via Redundant-Node Hardening for Reliable Applications

Layout-Hardened 18T SRAM With High Reliability and Low Power for Aerospace Applications

Replacement-Based Key-Controlled Circuits: A New Lightweight Logic-Locking Technique to Prevent the SAT Attack and Its Variants

SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF

Approximate multiplier design and error estimate model based on partial carry truncation

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications

基于相关性分离的逻辑电路敏感门定位算法

A radiation-hardened 20T SRAM Cell with high reliability and low power consumption

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks

A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs

Low-power and high-speed SRAM cells for double-node-upset recovery

A highly reliable and low-power cross-coupled 18T SRAM cell

A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design

A secure scan architecture using parallel latch-based lock

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation

Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture

FPGA implementation and image encryption application of a new PRNG based on a memristive Hopfield neural network with a special activation gradient

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory

A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design

Preventing Scan-Based Side-Channel Attacks by Scan Obfuscating with a Configurable Shift Register

A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults

An Efficient Degraded Deductive Fault Simulator for Small-Delay Defects

低延迟低电压电流比较器

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks

“新工科”背景下非计算机类专业计算机网络课程教学探索

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory

用KM算法增强测试集的频谱主分量

成果导向的信息类专业电路系列课程改革研究

Reliability evaluation of logic circuits based on transient faults propagation metrics

A novel test data compression approach based on bit reversion

Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar

Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

基于伯努利分布的逻辑电路可靠度计算方法

一种用于测试数据压缩的自适应EFDR编码方法

基于差错传播概率矩阵的时序电路软错误可靠性评估

逻辑电路软错误可靠性评估方法研究

一种用于测试数据压缩的改进型EFDR编码方法

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

An efficient small‐delay faults simulator based on critical path tracing

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

Harzard-Based ATPG for Improving Delay Test Quality

考虑信号相关性的逻辑电路可靠度计算方法

一种将测试集嵌入到Test-per-Clock位流中的方法

An effective logic BIST scheme based on LFSR-reseeding and TVAC

An effective deterministic test generation for test-per-clock testing

An Efficient Reliability Estimation Method for Gate-level Circuit: An Efficient Reliability Estimation Method for Gate-level Circuit

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Low power logic BIST with high test effectiveness

An Efficient Mixed-Mode BIST Scheme for Test-Per-Clock Testing

一种高效的小时延故障模拟方法

一种基于串行移位的测试数据生成方法

一种多扫描链混合测试数据压缩方法

波形模拟器关于组合电路中竞争冒险的应用

浅谈如何在计算机专业教学中培养创新型人才

Method to test redundant stuck-at faults considering logic gates' delay

New Test Generation Scheme Based on Serial Shifter

独立学院计算机科学与技术专业人才培养模式研究

Embedding N-Detect Test Set into Controlled Bits Stream

基于VHDL的非系统前馈卷积码编码器设计

用全速电流测试方法检测PIC12F509微处理器

Using at Speed Current Testing Method to Test PIC12F509 Microprocessor

Test Pattern Generation Algorithm Based on CUT's Feedback

一种检测冗余故障的瞬态电流测试方法

时延故障测试产生算法与IDDT测试实验研究

一种基于IDDT测试的时延故障测试产生算法

A Method to Test Redundant Faults Using IDDT Testing