陈建利｜复旦大学｜学者主页

2026

Layer-Aware Timing-Driven Global Routing for Advanced Technology Nodes

Zhaoyi Wu, Haishan Huang, Benchao Zhu, Jianli Chen, Zhifeng Lin

IEEE International Symposium on Circuits and Systems proceedings

DOI

2026

RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping

Ruiyuan Guo, Zexu Zhang, Chang Liu, Da Tang, Weiqi Shen, Haodong Lu, Xiqiong Bai, Kun Wang, Jianli Chen, Jie Yu

DOI

2026

An Adaptive Cost-based Via and Congestion Co-optimization Framework for VLSI Global Routing

Zhaoyi Wu, Haishan Huang, Jianli Chen, Zhifeng Lin

DOI

2026

An Analytical Placement Framework for Advanced Hybrid-Row-Height Circuit Designs

Benchao Zhu, Yuan Wen, Jiarui Chen, Jianli Chen, Zhifeng Lin

ACM Transactions on Design Automation of Electronic Systems

DOI

2026

A Co-optimization Framework for Resolving Via Coloring Conflict in Multiple Patterning Lithography

Junqi Wang, Haodong Lu, Jianli Chen, Kun Wang

ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI

2026

A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking

Benchao Zhu, Jiawei Li, Yang Liu, Jianli Chen, Keren Zhu

ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI

2025

3D CoSim: Coupled Operator Learning-Based Co-Simulator for Transferable 3D-IC Analysis

Youran Wu, Shunjie Chang, Jianli Chen, Jun Wei Yu, Kun Wang

DOI

2025

3D DRC: Design Rule Checking for 3D IC with U-Net-based Non-Manhattan Optimization

Shunjie Chang, Youran Wu, Jianli Chen, Jun Yu, Kun Wang

DOI

2025

Obstacle-Avoiding X-Architecture Bounded-Skew Tree Algorithm Under Timing Slack Constraints

Genggeng Liu, Ren Lu, Yuhan Zhu, Zhifeng Lin, Chuandong Chen, Min Gan, Jianli Chen, Wenzhong Guo

IEEE Transactions on Systems Man and Cybernetics Systems

DOI

2025

Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance

Faxian Sun, Runzhou Zhang, Zhenyu Liu, Heng Liao, Zhinan Qin, Jianli Chen, Jun Wei Yu, Kun Wang

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification

Shuai Zhou, Huinan Tian, Sisi Meng, Jianli Chen, Jun Yu, Kun Wang

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

Multi-Bit Flip-Flop Based Timing and Power Optimization under Advanced Technology Nodes

Tingxuan Gong, Wenxu Ruan, Dongwei Tan, Zhendong He, Zhifeng Lin, Jianli Chen

IEEE International Symposium on Circuits and Systems proceedings

DOI

2025

Legalization Framework with Design Rule Constraints Enhanced by Monte-Carlo-Based Cell Priority Optimization

Benchao Zhu, Guohao Chen, Jiawei Li, Peng Zou, Haokai Sun, Zhifeng Lin, Jianli Chen

IEEE International Symposium on Circuits and Systems proceedings

DOI

2025

A Matching-Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints

Chuandong Chen, Disi Lin, Qinghai Liu, Huan He, Zhifeng Lin, Genggeng Liu, Jianli Chen, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints

Hao Gu, Jian Hui Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian Splatting

Yuanfang Wang, Yu Li, Jianli Chen, Jun Yu, Kun Wang

DOI

2025

AttentionLib: A Scalable Optimization Framework for Automated Attention Acceleration on FPGA

Zhenyu Liu, Xilang Zhou, Faxian Sun, Jianli Chen, Jun Wei Yu, Kun Wang

DOI

2025

ToMamba: Towards Token-Efficient Mamba Architecture on FPGA

Kejia Shi, Yue Cao, Yuhang Du, Jianli Chen, Jun Yu, Kun Wang

DOI

2025

Analytical Layer Assignment with Simulated Annealing Refinement

Zhijie Cai, Min Wei, Peng Zou, Xiqiong Bai, Zhifeng Lin, Jianli Chen

IEEE International Symposium on Circuits and Systems proceedings

DOI

2025

TaiChi: Efficient Execution for Multi-DNNs Using Graph-Based Scheduling

Xilang Zhou, Haodong Lu, Tianchen Wang, Zhuoheng Wan, Jianli Chen, Jun Wei Yu, Kun Wang

DOI

2024

Global and Local Attention-Based Inception U-Net for Static IR Drop Prediction

Yilu Chen, Zhijie Cai, Min Wei, Zhifeng Lin, Jianli Chen

Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design

DOI

2024

Subgraph Matching with Diversity Handling and Its Applications to PCB Placement

Chuandong Chen, Haiming Lin, Miaodi Su, Huan He, Jianli Chen, Ziran Zhu

International Symposium of Electronics Design Automation (ISEDA)

DOI

2024

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction

Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu, Jianli Chen, Jun Yang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2024

An Extensible Legalization Framework for Multiple Physical Design Constraints

Jiawei Li, Peng Zou, Min Wei, Guohao Chen, Zhifeng Lin, Jun Yu, Jianli Chen

DOI

2024

Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB

Disi Lin, Chuandong Chen, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin, Jianli Chen

Integration

DOI

2024

A fast and high-performance global router with enhanced congestion control

Xiqiong Bai, Yilu Chen, Zhifeng Lin, Min Wei, Zhijie Cai, Ziran Zhu, Jianli Chen

Integration

DOI

2024

Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion

Jihai Meng, Shaohong Weng, Zhijie Cai, Yilu Chen, Zhifeng Lin, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2024

Late Breaking Results: Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints

Benchao Zhu, Zheng Zeng, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2024

Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping

Yilu Chen, Zhifeng Lin, Xiaojian Liang, Zhijie Cai, Xiqiong Bai, Jianli Chen

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2024

Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs

Yuan Wen, Benchao Zhu, Zhifeng Lin, Jianli Chen

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2024

An analytical timing-driven placer for modern heterogeneous FPGAs

Zhifeng Lin, Yilu Chen, Yanyue Xie, Chuandong Chen, Jun Wei Yu, Jianli Chen

The Journal of Supercomputing

DOI

2024

An analytical placement algorithm with looking-ahead routing topology optimization

Min Wei, Xingyu Tong, Zhijie Cai, Peng Zou, Zhifeng Lin, Jianli Chen

Integration

DOI

2024

Electrostatics-Based Analytical Global Placement for Timing Optimization

Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao‐Wen Chang

DOI

2023

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints

Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2023

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks

Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Wei Yu, Kun Wang

DOI

2023

An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs

Zijun Li, Ziran Zhu, Huan He, Jianli Chen

Integration

DOI

2023

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks

Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang

International Conference on Field Programmable Logic and Applications (FPL)

DOI

2023

An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting

Ziran Zhu, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang

IEEE Transactions on Circuits & Systems II Express Briefs

DOI

2023

Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints

Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2023

A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints

Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2023

PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration

Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Wei Yu, Jianli Chen, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2023

Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints

Guohao Chen, Zheng Zeng, Benchao Zhu, Jiawei Li, Kun Wang, Jun Wei Yu, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2023

Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints

Peng Zou, Guohao Chen, Zhifeng Lin, Jun Yu, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2023

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning

Yueyin Bai, Hao Zhou, Ruiqi Chen, Kuangjie Zou, Jialin Cao, Haoyang Zhang, Jianli Chen, Jun Yu, Kun Wang

International Conference on Communications

DOI

2023

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication

Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Jianli Chen, Jun Wei Yu, Kun Wang

IEEE International Symposium on Circuits and Systems proceedings

DOI

2023

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks

Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang

IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)

DOI

2023

Efficient Global Optimization for Large Scaled Ordered Escape Routing

Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2022

A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints

Ziran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, Jun Yang

DOI

2022

Virtual-Path-Based Timing Optimization for VLSI Global Placement

Weijie Chen, Haishan Huang, Min Wei, Peng Zou, Jianli Chen

IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

DOI

2022

An Efficient Global Router for Large-scale Congestion-driven Routing

Haishan Huang, Weijie Chen, Zhijie Cai, Jiarong Huang, Jianli Chen

IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

DOI

2022

Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints

Peng Zou, Zhijie Cai, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2022

High-performance placement for large-scale heterogeneous FPGAs with clock constraints

Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Lan Yang, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2022

Subgraph matching based reference placement for PCB designs

Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2022

Analytical Optimization Method for VLSI Global Placement

Weijie Chen, Haishan Huang, Zhipeng Huang, Jianli Chen

China Semiconductor Technology International Conference (CSTIC)

DOI

2022

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Qi Long Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, Bei Yu

ACM Transactions on Design Automation of Electronic Systems

DOI

2022

Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects

Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2022

High-Correlation 3D Routability Estimation for Congestion-guided Global Routing

Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao‐Wen Chang

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2022

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Wei Yu, Yao‐Wen Chang

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2021

Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints

Jianli Chen, Zhifeng Lin, Yanyue Xie, Wenxing Zhu, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2021

Timing-Aware Fill Insertions With Design-Rule and Density Constraints

Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Wei Yu, Wenxing Zhu, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2021

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration

Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Wei Yu, Bei Yu

Proceedings - ACM IEEE Design Automation Conference

DOI

2021

Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement

Peng Zou, Zhifeng Lin, Chenyue Ma, Jun Wei Yu, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2021

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints

Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Wei Yu, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2021

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

Xiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2021

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper

Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo

DOI

2021

CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs

Chenyue Ma, Yifeng Xiao, Sifei Wang, Jun Wei Yu, Jianli Chen

IEEE International Conference on ASIC (ASICON)

DOI

2021

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness

Zhifeng Lin, Yanyue Xie, Peng Zou, Sifei Wang, Jun Wei Yu, Jianli Chen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2021

Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints

Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2021

Topology‐Aware Bus Routing in Complex Networks of Very‐Large‐Scale Integration with Nonuniform Track Configurations and Obstacles

Ziran Zhu, Zhipeng Huang, Jianli Chen, Longkun Guo

Complexity

DOI

2021

Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection

Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2020

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification

Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Wei Yu, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2020

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells

Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Wei Yu, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2020

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation

Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao‐Wen Chang

Proceedings - ACM IEEE Design Automation Conference

DOI

2020

Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs

Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Wei Yu, Jianli Chen

Proceedings - ACM IEEE Design Automation Conference

DOI

2020

A non-gaussian adaptive importance sampling method for high-dimensional and multi-failure-region yield analysis

Xiao Shi, Hao Yan, Chuwen Li, Jianli Chen, Longxing Shi, Lei He

DOI

2020

Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints

Jianli Chen, Yao-Wen Chang, Yen-Yi Wu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2020

Analytical Placement Considering the Electron-Beam Fogging Effect

Jianli Chen, Yao-Wen Chang, Yu-Chen Huang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2020

Mixed-Cell-Height Legalization Considering Technology and Region Constraints

Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2020

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy‐Yen Kuo

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2020

An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning

Zhipeng Huang, Zhifeng Lin, Ziran Zhu, Jianli Chen

IEEE Access

DOI

2019

Timing-Aware Fill Insertions with Design-Rule and Density Constraints

Tingshen Lan, Xingquan Li, Jianli Chen, Jun Wei Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao‐Wen Chang

DOI

2016

基于多阶段拆线重布的总体布线算法

朱自然，陈建利，朱文兴

《计算机辅助设计与图形学学报》

精选作品

期刊论文

Layer-Aware Timing-Driven Global Routing for Advanced Technology Nodes

RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage Mapping

An Adaptive Cost-based Via and Congestion Co-optimization Framework for VLSI Global Routing

An Analytical Placement Framework for Advanced Hybrid-Row-Height Circuit Designs

A Co-optimization Framework for Resolving Via Coloring Conflict in Multiple Patterning Lithography

A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking

3D CoSim: Coupled Operator Learning-Based Co-Simulator for Transferable 3D-IC Analysis

3D DRC: Design Rule Checking for 3D IC with U-Net-based Non-Manhattan Optimization

Obstacle-Avoiding X-Architecture Bounded-Skew Tree Algorithm Under Timing Slack Constraints

Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance

XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification

Multi-Bit Flip-Flop Based Timing and Power Optimization under Advanced Technology Nodes

Legalization Framework with Design Rule Constraints Enhanced by Monte-Carlo-Based Cell Priority Optimization

A Matching-Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints

Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints

FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian Splatting

AttentionLib: A Scalable Optimization Framework for Automated Attention Acceleration on FPGA

ToMamba: Towards Token-Efficient Mamba Architecture on FPGA

Analytical Layer Assignment with Simulated Annealing Refinement

TaiChi: Efficient Execution for Multi-DNNs Using Graph-Based Scheduling

Global and Local Attention-Based Inception U-Net for Static IR Drop Prediction

Subgraph Matching with Diversity Handling and Its Applications to PCB Placement

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction

An Extensible Legalization Framework for Multiple Physical Design Constraints

Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB

A fast and high-performance global router with enhanced congestion control

Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion

Late Breaking Results: Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints

Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping

Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs

An analytical timing-driven placer for modern heterogeneous FPGAs

An analytical placement algorithm with looking-ahead routing topology optimization

Electrostatics-Based Analytical Global Placement for Timing Optimization

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks

An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks

An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting

Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints

A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints

PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration

Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints

Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks

Efficient Global Optimization for Large Scaled Ordered Escape Routing

A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints

Virtual-Path-Based Timing Optimization for VLSI Global Placement

An Efficient Global Router for Large-scale Congestion-driven Routing

Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints

High-performance placement for large-scale heterogeneous FPGAs with clock constraints

Subgraph matching based reference placement for PCB designs

Analytical Optimization Method for VLSI Global Placement

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects

High-Correlation 3D Routability Estimation for Congestion-guided Global Routing

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints

Timing-Aware Fill Insertions With Design-Rule and Density Constraints

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration

Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper

CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness

Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints

Topology‐Aware Bus Routing in Complex Networks of Very‐Large‐Scale Integration with Nonuniform Track Configurations and Obstacles

Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation

Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs

A non-gaussian adaptive importance sampling method for high-dimensional and multi-failure-region yield analysis

Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints

Analytical Placement Considering the Electron-Beam Fogging Effect

Mixed-Cell-Height Legalization Considering Technology and Region Constraints