鲁金铭｜南京大学｜学者主页

2026

HoloLUT: An Efficient LUT-Based Engine via Holistic Data Processing for Low-bit LLM Inference

Hui Wang, Wenlian Ma, Jinming Lu, Jun Lin

ACM Great Lakes Symposium on VLSI (GLSVLSI)

2026

SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention

Wentao Xu, Yuxuan Zhang, Rongzhou Zhu, Xiang Wu, Zehao Wang, Weilin Li, Jiaxiang Wang, Chunyang Du, Yuanlu Gao, Zhanxiang Gao, Fengdong Qu, Jinming Lu, Li Du

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

ZOAF: Towards Efficient Zeroth-Order Optimization for Analog/RF Circuit Design

Li-Yan Tan, Ye-Quan Zhao, Jinming Lu, Benjamin F. Jamroz, Ari D. Feldman, Zheng Zhang

arXiv.org

DOI

2025

CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model

Jinming Lu, Minghao She, Wendong Mao, Zhongfeng Wang

IEEE International Symposium on Circuits and Systems proceedings

DOI

2025

Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization

Jia-Yi Tian, Jinming Lu, Hai Li, Xiangwei Wang, C. Hao, Ian Young, Zheng Zhang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training

Jinming Lu, Jia-Yi Tian, Hai Li, Ian Young, Zheng Zhang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators

Jinsong Zhang, Minghe Li, Jia-Yi Tian, Jinming Lu, Zheng Zhang

arXiv.org

DOI

2025

FLAT-LLM: Fine-grained Low-rank Activation Space Transformation for Large Language Model Compression

Jia-Yi Tian, Ryan Solgi, Jinming Lu, Yifan Yang, Hai Li, Zheng Zhang

Conference of the European Chapter of the Association for Computational Linguistics

DOI

2025

Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers

Jinming Lu, Jia-Yi Tian, Ye-Quan Zhao, Hai Li, Zheng Zhang

arXiv.org

DOI

2023

An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization

Haikuo Shao, Jinming Lu, Meiqi Wang, Zhongfeng Wang

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2023

An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd

Hui Wang, Jinming Lu, Jun Ting Lin, Zhongfeng Wang

IEEE Computer Society Annual Symposium on VLSI

DOI

2023

WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd

Jinming Lu, Hui Wang, Jun Ting Lin, Zhongfeng Wang

IEEE Transactions on Circuits and Systems I Regular Papers

DOI

2022

THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration

Jinming Lu, Jian Huang, Zhongfeng Wang

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2022

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization

Jinming Lu, Chao Ni, Zhongfeng Wang

IEEE Transactions on Neural Networks and Learning Systems

DOI

2022

An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity

Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Ting Lin

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

DOI

2022

An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity

Jian Huang, Jinming Lu, Zhongfeng Wang

IEEE International Symposium on Circuits and Systems proceedings

DOI

2021

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training

Haikuo Shao, Jinming Lu, Jun Ting Lin, Zhongfeng Wang

IEEE Computer Society Annual Symposium on VLSI

DOI

2021

A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA

Tongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang

IEEE Computer Society Annual Symposium on VLSI

DOI

2020

Evaluations on Deep Neural Networks Training Using Posit Number System

Jinming Lu, Chao Fang, Mingyang Xu, Jun Ting Lin, Zhongfeng Wang

IEEE Transactions on Computers

DOI

2020

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks

Chao Ni, Jinming Lu, Jun Ting Lin, Zhongfeng Wang

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

DOI

2020

A Reconfigurable DNN Training Accelerator on FPGA

Jinming Lu, Jun Ting Lin, Zhongfeng Wang

SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems

DOI

2019

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory

Meiqi Wang, Zhisheng Wang, Jinming Lu, Jun Ting Lin, Zhongfeng Wang

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

DOI

2019

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding

Siyuan Lu, Jinming Lu, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International Workshop on Signal Processing Systems (SiPS)

DOI

2019

Training Deep Neural Networks Using Posit Number System

Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Ting Lin, Zhongfeng Wang, Li Du

IEEE International System-on-Chip Conference (SOCC)

DOI

2019

A Hardware-Oriented and Memory-Efficient Method for CTC Decoding

Siyuan Lu, Jinming Lu, Jun Ting Lin, Zhongfeng Wang

IEEE Access

DOI

鲁金铭

精选作品

期刊论文

HoloLUT: An Efficient LUT-Based Engine via Holistic Data Processing for Low-bit LLM Inference

SATurbine: A Multicore Transformer Accelerator With Gated Broadcast for Efficient Dynamic Sparse Attention

ZOAF: Towards Efficient Zeroth-Order Optimization for Analog/RF Circuit Design

CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model

Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization

FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators

FLAT-LLM: Fine-grained Low-rank Activation Space Transformation for Large Language Model Compression

Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers

An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization

An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd

WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd

THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization

An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity

An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training

A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA

Evaluations on Deep Neural Networks Training Using Posit Number System

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks

A Reconfigurable DNN Training Accelerator on FPGA

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding

Training Deep Neural Networks Using Posit Number System

A Hardware-Oriented and Memory-Efficient Method for CTC Decoding

研究方向