曹宇

2026

EGO: Efficient Compression of Unstructured Sparse DNNs for Compute-in-Memory based on Graph Minimum-Cost Matching Optimization

Design, Automation and Test in Europe

DOI

2026

73‐2: Invited Paper: High‐Performance Carbon Nanotube Thin Film Transistors Enabled by Atomic Layer Etching Process for Display Driving

SID Symposium Digest of Technical Papers

DOI

2026

Monolithic Integration of Carbon Nanotube-Based Complementary Field-Effect Transistors with 3D-Stacked Photodiodes for Unified Sensing and Computing

ACS Nano

DOI

2025

一种超低压差防倒灌线性稳压器设计

《微电子学》

DOI

2025

Micro-LED Microdisplays Driven by Carbon Nanotube Active-Matrix Backplanes

ACS Nano

DOI

2024

Investigation and Improvement of the Bias Temperature Instability in Carbon Nanotube Transistors

Advanced Electronic Materials

DOI

2023

Digital-Assisted Analog In-Memory Computing with RRAM Devices

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)

DOI

2023

Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA

ACM Transactions on Reconfigurable Technology and Systems

DOI

2023

FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix

Design, Automation and Test in Europe

DOI

2023

Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention

International Symposium on Circuits and Systems

DOI

2023

Improving the Performance of Aligned Carbon Nanotube-Based Transistors by Refreshing the Substrate Surface.

ACS Applied Materials and Interfaces

DOI

2023

38.4: High Performance Carbon Nanotube Thin Film Transistors for miniߚLED Driving

SID Symposium Digest of Technical Papers

DOI

2022

Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration

IEEE transactions on computers

DOI

2022

Efficient continual learning at the edge with progressive segmented training

Neuromorph. Comput. Eng.

DOI

2022

XMA: A Crossbar-aware Multi-task Adaption Framework via Shift-based Mask Learning Method

Design Automation Conference

DOI

2022

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2022

Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder

Asilomar Conference on Signals, Systems and Computers

DOI

2022

XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning

Design, Automation and Test in Europe

DOI

2022

Synergistic passivation and stepped-dimensional perovskite analogs enable high-efficiency near-infrared light-emitting diodes

Nature Communications

DOI

2022

Low Dark Current and Performance Enhanced Perovskite Photodetector by Graphene Oxide as an Interfacial Layer

Nanomaterials

DOI

2022

Defects Passivation Strategy for Efficient and Stable Perovskite Solar Cells

Advanced Materials Interfaces

DOI

2022

A high-performance polarization-sensitive and stable self-powered UV photodetector based on a dendritic crystal lead-free metal-halide CsCu2I3/GaN heterostructure.

Materials Horizons

DOI

2022

Recent defect passivation drifts and role of additive engineering in perovskite photovoltaics

Nano Energy

DOI

2022

Progress on the stability and encapsulation techniques of perovskite solar cells

Organic electronics

DOI

2021

System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration

International Conference on ASIC

DOI

2021

Interconnect-Centric Benchmarking of In-Memory Acceleration for DNNS

China Semiconductor Technology International Conference

DOI

2021

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

ACM Transactions on Embedded Computing Systems

DOI

2021

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression

International Conference on Field-Programmable Logic and Applications

DOI

2021

Design Limits of In-Memory Computing: Beyond the Crossbar

IEEE Electron Devices Technology and Manufacturing Conference

DOI

2021

RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy

arXiv.org

2021

Evolutionary NAS in Light of Model Stability for Accurate Continual Learning

IEEE International Joint Conference on Neural Network

DOI

2021

Robust RRAM-based In-Memory Computing in Light of Model Stability

IEEE International Reliability Physics Symposium

DOI

2021

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks

ACM Journal on Emerging Technologies in Computing Systems

DOI

2021

Alternate Model Growth and Pruning for Efficient Training of Recommendation Systems

International Conference on Machine Learning and Applications

DOI

2021

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA

Symposium on Field Programmable Gate Arrays

DOI

2020

一种时间交织ADC采样时间误差校正方法

《微电子学》

DOI

2020

Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation

Design Automation Conference

DOI

2020

DAT-RNN: Trajectory Prediction with Diverse Attention

International Conference on Machine Learning and Applications

DOI

2020

GAR: Graph Assisted Reasoning for Object Detection

IEEE Workshop/Winter Conference on Applications of Computer Vision

DOI

2020

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

DOI

2020

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

DOI

2020

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs

IEEE design & test

DOI

2020

Accurate Inference With Inaccurate RRAM Devices: A Joint Algorithm-Design Solution

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

DOI

2020

Noise-based Selection of Robust Inherited Model for Accurate Continual Learning

2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)

DOI

2020

Deep Neural Network Training Accelerator Designs in ASIC and FPGA

International SoC Design Conference

DOI

2020

Online Knowledge Acquisition with the Selective Inherited Model

IEEE International Joint Conference on Neural Network

DOI

2020

Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2020

Performance Modeling for CNN Inference Accelerators on FPGA

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2020

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

ACM Great Lakes Symposium on VLSI

DOI

2020

Efficient and Modularized Training on FPGA for Real-time Applications

International Joint Conference on Artificial Intelligence

DOI

2020

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2019

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain (vol 12, 891, 2018)

2019

Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2)

ACM Journal on Emerging Technologies in Computing Systems

DOI

2019

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2019

Automatic Compiler Based FPGA Accelerator for CNN Training

International Conference on Field-Programmable Logic and Applications

DOI

2019

Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

Frontiers in Neuroscience

DOI

2019

Towards Efficient Neural Networks On-A-Chip: Joint Hardware-Algorithm Approaches

China Semiconductor Technology International Conference

DOI

2019

Structural Pruning in Deep Neural Networks: A Small-World Approach

arXiv.org

2019

Guest Editors’ Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning

ACM Journal on Emerging Technologies in Computing Systems

DOI

2018

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

Frontiers in Neuroscience

DOI

2018

Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning

ACM Journal on Emerging Technologies in Computing Systems

DOI

2018

Oriented Quasi‐2D Perovskites for High Performance Optoelectronic Devices

Advances in Materials

DOI

2018

Efficient charge separation at multiple quantum well perovskite/PCBM interface

Applied Physics Letters

DOI

2018

Review on flexible photonics/electronics integrated devices and fabrication strategy

Science China Information Sciences

DOI

2018

Efficient Perovskite Solar Cells Fabricated by Co Partially Substituted Hybrid Perovskite

Advanced Energy Materials

DOI

2018

Minimising efficiency roll-off in high-brightness perovskite light-emitting diodes

Nature Communications

DOI

2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Integr.

DOI

2017

Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning

ACM Journal on Emerging Technologies in Computing Systems

DOI

2017

Visual Saliency Application in Object Detection for Search Space Reduction

2017

Sky-blue perovskite light-emitting diodes based on quasi-two-dimensional layered perovskites

DOI

2017

Efficient Red Perovskite Light‐Emitting Diodes Based on Solution‐Processed Multiple Quantum Wells

Advances in Materials

DOI

2017

Inhomogeneous degradation in metal halide perovskites

DOI

2017

Benzylamine‐Treated Wide‐Bandgap Perovskite with High Thermal‐Photostability and Photovoltaic Performance

DOI

2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Symposium on Field Programmable Gate Arrays

DOI

2016

Hardware-efficient learning with feedforward inhibition

IEEE International Nanoelectronics Conference

DOI

2016

600 V/ $1.7~\Omega$ Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor

IEEE Electron Device Letters

DOI

2016

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

International Conference on Field-Programmable Logic and Applications

DOI

2016

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

DOI

2016

High-performance face detection with CPU-FPGA acceleration

International Symposium on Circuits and Systems

DOI

2016

Carbon Nanotube Macroelectronics for Active Matrix Polymer-Dispersed Liquid Crystal Displays.

ACS Nano

DOI

2016

An Experimental Demonstration of GaN CMOS Technology

IEEE Electron Device Letters

DOI

2016

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2016

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2016

Ultralow-Leakage AlGaN/GaN High Electron Mobility Transistors on Si With Non-Alloyed Regrown Ohmic Contacts

IEEE Electron Device Letters

DOI

2015

The impact of defect scattering on the quasi-ballistic transport of nanoscale conductors

DOI

2015

Method and apparatus to enhance read accuracy in resistive crosspoint array

2015

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Design, Automation and Test in Europe

DOI

2015

On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

IEEE transactions on nanotechnology

DOI

2015

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology

IEEE International Reliability Physics Symposium

DOI

2015

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication

Journal of Computational Science and Technology

DOI

2015

Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings

ICCD

DOI

2015

Exploiting resistive cross-point array for compact design of physical unclonable function

IEEE International Symposium on Hardware Oriented Security and Trust

DOI

2015

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2015

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

International Electron Devices Meeting

DOI

2015

Accelerated Aging in Analog and Digital Circuits With Feedback

IEEE transactions on device and materials reliability

DOI

2015

On-chip Sparse Learning with Resistive Cross-point Array Architecture

ACM Great Lakes Symposium on VLSI

DOI

2015

Finite-point method for efficient timing characterization of sequential elements

Integr.

DOI

2015

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

DOI

2015

A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching

ACM Trans. Design Autom. Electr. Syst.

DOI

2015

RRAM-based PUF : Design and Applications in Cryptography

2015

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits

ICCD

DOI

2015

Programming strategies to improve energy efficiency and reliability of ReRAM memory systems

IEEE Workshop on Signal Processing Systems

DOI

2015

1.9-kV AlGaN/GaN Lateral Schottky Barrier Diodes on Silicon

IEEE Electron Device Letters

DOI

2014

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors

Nature Communications

DOI

2014

Native and process induced defects in GaN films grown on Si substrates probed using a monoenergetic positron beam

International Workshop on Junction Technology

DOI

2014

Novel voltage step stress (VSS) technique for fast lifetime prediction of hot carrier degradation

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI

2014

Statistical analysis of random telegraph noise in digital circuits

Asia and South Pacific Design Automation Conference

DOI

2014

A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram

Journal of Signal Processing Systems

DOI

2014

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

IEEE Workshop on Signal Processing Systems

DOI

2014

Where is the Achilles Heel under Circuit Aging

IEEE Computer Society Annual Symposium on VLSI

DOI

2014

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning

2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings

DOI

2014

Charge trapping in aligned single-walled carbon nanotube arrays induced by ionizing radiation exposure

DOI

2014

AlGaN/GaN MIS-HEMT on silicon with steep sub-threshold swing < 60 mV/dec over 6 orders of drain current swing and relation to traps

IEEE Silicon Nanoelectronics Workshop

DOI

2014

Compact modeling of STT-MTJ devices

DOI

2014

Cross-Layer Modeling and Simulation of Circuit Reliability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2014

Aging Statistics Based on Trapping/Detrapping: Compact Modeling and Silicon Validation

IEEE transactions on device and materials reliability

DOI

2014

BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation

Design Automation Conference

DOI

2014

Diagnosing bias runaway in analog/mixed signal circuits

IEEE International Reliability Physics Symposium

DOI

2013

GaN on Silicon Growth by MOCVD: A Mechanistic Approach to Wafer Scaling

2013

Numerical study on effects of random dopant fluctuation in double gate tunneling FET

2013 IEEE International Conference of Electron Devices and Solid-state Circuits

DOI

2013

Nanowire Channel InAlN/GaN HEMTs With High Linearity of <formula formulatype="inline"> <tex Notation="TeX">$g_{\rm m}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$f_{\rm T}$</tex></formula>

IEEE Electron Device Letters

DOI

2013

Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction

IEEE International Reliability Physics Symposium

DOI

2013

Quaternary Barrier InAlGaN HEMTs With $f_{T}/f_{\max}$ of 230/300 GHz

IEEE Electron Device Letters

DOI

2013

Dispersion-free operation in InAlN-based HEMTs with ultrathin or no passivation

2013 IEEE International Electron Devices Meeting

DOI

2013

Compact modeling of parameter variations of nanoscale CMOS due to random dopant fluctuation

2013

Effect of electron irradiation on AlGaN/GaN and InAlN/GaN heterojunctions

DOI

2013

Assessment of Circuit Optimization Techniques Under NBTI

IEEE design & test

DOI

2013

Effect of buffer structures on AlGaN/GaN high electron mobility transistor reliability

DOI

2013

Failure Analysis of Asymmetric Aging Under NBTI

IEEE transactions on device and materials reliability

DOI

2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

IET Circuits Devices Syst.

DOI

2013

Compact Modeling of Statistical BTI Under Trapping/Detrapping

IEEE Transactions on Electron Devices

DOI

2013

ACE: A robust variability and aging sensor for high-k/metal gate SoC

European Solid-State Device Research Conference

DOI

2013

Polarization-Induced GaN-on-Insulator E/D Mode p-Channel Heterostructure FETs

IEEE Electron Device Letters

DOI

2013

Device Delay in GaN Transistors Under High Drain Bias Conditions

IEEE Electron Device Letters

DOI

2013

High linearity nanowire channel GaN HEMTs

Device Research Conference

DOI

2013

Compact modeling of STT-MTJ for SPICE simulation

European Solid-State Device Research Conference

DOI

2013

NBTI-aware circuit node criticality computation

JETC

DOI

2012

InGaN Channel High-Electron-Mobility Transistors with InAlGaN Barrier and fT/fmax of 260/220 GHz

DOI

2012

Statistical aging under dynamic voltage scaling: A logarithmic model approach

Proceedings of the IEEE Custom Integrated Circuits Conference

DOI

2012

Physics matters: Statistical aging prediction under trapping/detrapping

DAC Design Automation Conference 2012

DOI

2012

A charge based non-quasi-static transient model for SOI MOSFETs

2012

Hierarchical modeling of Phase Change memory for reliable design

ICCD

DOI

2012

Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques

IEEE Workshop on Signal Processing Systems

DOI

2012

Effect of buffer layer structure on electrical and structural properties of AlGaN/GaN high electron mobility transistors

DOI

2012

Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors

IEEE Design & Test of Computers

DOI

2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

IEEE Computer Society Annual Symposium on VLSI

DOI

2012

The potential of Fe-FET for robust design under variations: A compact modeling study

Microelectronics Journal

DOI

2012

MBE-Regrown Ohmics in InAlN HEMTs With a Regrowth Interface Resistance of 0.05 $\Omega\cdot\hbox{mm}$

IEEE Electron Device Letters

DOI

2012

Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2012

Impact of $\hbox{Al}_{2}\hbox{O}_{3}$ Passivation Thickness in Highly Scaled GaN HEMTs

IEEE Electron Device Letters

DOI

2012

Degradation of dc characteristics of InAlN/GaN high electron mobility transistors by 5 MeV proton irradiation

DOI

2012

InGaN channel high electron mobility transistor structures grown by metal organic chemical vapor deposition

DOI

2012

Controlled synthesis of AlN/GaN multiple quantum well nanowire structures and their optical properties.

Nano letters (Print)

DOI

2012

Leakage reduction through optimization of regular layout parameters

Microelectronics Journal

DOI

2012

Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

EURASIP Journal on Advances in Signal Processing

DOI

2012

Ultrathin Body GaN-on-Insulator Quantum Well FETs With Regrown Ohmic Contacts

IEEE Electron Device Letters

DOI

2012

Proton irradiation energy dependence of dc and rf characteristics on InAlN/GaN high electron mobility transistors

DOI

2012

Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

IEEE International Reliability Physics Symposium

DOI

2012

193 nm excimer laser lift-off for AlGaN/GaN high electron mobility transistors

DOI

2012

In‐situ X‐ray photoelectron spectroscopy of trimethyl aluminum and water half‐cycle treatments on HF‐treated and O3‐oxidized GaN substrates

DOI

2012

Proton irradiation energy dependence of dc and rf characteristics on InAlN/GaN high electron mobility transistors [J. Vac. Sci. Technol. B 30, 041206 (2012)]

DOI

2012

Simulation and experimental study of ArF 193 nm laser lift-off AlGaN/GaN high electron mobility transistors

DOI

2012

Design benchmarking to 7nm with FinFET predictive technology models

International Symposium on Low Power Electronics and Design

DOI

2012

An analytical approach to efficient circuit variability analysis in scaled CMOS design

IEEE International Symposium on Quality Electronic Design

DOI

2012

Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM

IEEE Workshop on Signal Processing Systems

DOI

2012

Modeling of Dynamic Threshold Voltage of High K Gate Stack and Application in FinFET Reliability Simulation

2011

A TDC-based test platform for dynamic circuit aging characterization

IEEE International Reliability Physics Symposium

DOI

2011

Effects of silicon nitride passivation on isolation-blocking voltage in algan/gan high electron mobility transistors

DOI

2011

Intrinsic Variability and Reliability in Nano-CMOS

DOI

2011

Design sensitivity of Single Event Transients in scaled logic circuits

Design Automation Conference

DOI

2011

The impact of correlation between NBTI and TDDB on the performance of digital circuits

Midwest Symposium on Circuits and Systems

DOI

2011

210-GHz InAlN/GaN HEMTs With Dielectric-Free Passivation

IEEE Electron Device Letters

DOI

2011

Improved Off-State Stress Critical Voltage on AlGaN/GaN High Electron Mobility Transistors Utilizing Pt/Ti/Au Based Gate Metallization

DOI

2011

220-GHz Quaternary Barrier InAlGaN/AlN/GaN HEMTs

IEEE Electron Device Letters

DOI

2011

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2011

Comparison of dc performance of Pt/Ti/Au- and Ni/Au-Gated AlGaN/GaN High Electron Mobility Transistors

DOI

2011

Metal‐face InAlN/AlN/GaN high electron mobility transistors with regrown ohmic contacts by molecular beam epitaxy

DOI

2011

Failure diagnosis of asymmetric aging under NBTI

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2011

Correlation of no trouble found errors to Negative Bias Temperature Instability

2011 Aerospace Conference

DOI

2011

Predictive Technology Model for Robust Nanoelectronic Design

Integrated Circuits and Systems

DOI

2011

Ultra-scaled GaN HEMTs with AlN barrier

2011

Compact modeling of signal transients and integrity analysis for dispersionless interconnect

2011

Improved Off-State Stress Critical Voltage on AlGaN/GaN High Electron Mobility Transistors Utilizing Pt/Ti/Au Gate Structure

DOI

2011

Effects of proton irradiation on dc characteristics of InAlN/GaN high electron mobility transistors

DOI

2011

(Invited) The Resurgence of III-N Materials Development: AlInN HEMTs and GaN-on-Si

DOI

2011

Workload-Aware Neuromorphic Design of the Power Controller

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

DOI

2011

Programmable analog device array (PANDA): A platform for transistor-level analog reconfigurability

Design Automation Conference

DOI

2011

A workload-aware neuromorphic controller for dynamic power and thermal management

NASA/ESA Conference on Adaptive Hardware and Systems

DOI

2011

Improvement of fT in InAl(Ga)N barrier HEMTs by plasma treatments

Device Research Conference

DOI

2011

Subcritical barrier AlN/GaN E/D‐mode HFETs and inverters

DOI

2011

Si-Containing Recessed Ohmic Contacts and 210 GHz Quaternary Barrier InAlGaN High-Electron-Mobility Transistors

DOI

2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2011

Circuit-level delay modeling considering both TDDB and NBTI

IEEE International Symposium on Quality Electronic Design

DOI

2011

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2011

Improvement of Off-State Stress Critical Voltage by Using Pt-Gated AlGaN/GaN High Electron Mobility Transistors

DOI

2011

Predictive Modeling of Carbon Nanotube Devices

DOI

2011

Comparative study of E- and D-mode InAlN/AlN/GaN HEMTs with fT near 200 GHz

International Semiconductor Device Research Symposium

DOI

2010

Workload-aware neuromorphic design of low-power supply voltage controller

International Symposium on Low Power Electronics and Design

DOI

2010

Work-function engineering in novel high Al composition Al0.72Ga0.28N/AlN/GaN HEMTs

Device Research Conference

DOI

2010

Optimized self-tuning for circuit aging

Design, Automation and Test in Europe

DOI

2010

Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design

IEEE Design & Test of Computers

DOI

2010

A self-evolving design methodology for power efficient multi-core systems

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2010

High mobility two-dimensional electron gases in nitride heterostructures with high Al composition AlGaN alloy barriers

DOI

2010

Simulation of random telegraph Noise with 2-stage equivalent circuit

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2010

Study of AlN/GaN HEMTs: MBE growth, transport properties and device issues

2010

Threshold Voltage Control in $\hbox{Al}_{0.72} \hbox{Ga}_{0.28}\hbox{N/AlN/GaN}$ HEMTs by Work-Function Engineering

IEEE Electron Device Letters

DOI

2010

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2010

In-situ characterization and extraction of SRAM variability

Design Automation Conference

DOI

2010

Workload-adaptive process tuning strategy for power-efficient multi-core processors

International Symposium on Low Power Electronics and Design

DOI

2010

Random variability modeling and its impact on scaled CMOS circuits

DOI

2010

Short‐period AlN/GaN p‐type superlattices: hole transport use in p‐n junctions

DOI

2010

Improved Frequency Response of On-Chip Inductors With Patterned Magnetic Dots

IEEE Electron Device Letters

DOI

2010

On the bias dependence of time exponent in NBTI and CHC effects

IEEE International Reliability Physics Symposium

DOI

2010

Molecular Beam Epitaxy Regrowth of Ohmics in Metal-face AlN/GaN Transistors

2010

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2010

A computational method for optimal application specific lens control in microlithography

Advanced Lithography

DOI

2010

Compact modeling of Fe-FET and implications on variation-insensitive design

International Conference on Simulation of Semiconductor Processes and Devices

DOI

2010

Hierarchical Fault Response Modeling of Analog/RF Circuits by Gurusubrahmaniyan Subrahmaniyan Radhakrishnan A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science Approved November 2010 by the Graduate Supervisory Committee: Sule Ozev, Chair

2010

A resilience roadmap

Design, Automation and Test in Europe

DOI

2009

Pathfinding for 22nm CMOS designs using Predictive Technology Models

IEEE Custom Integrated Circuits Conference

DOI

2009

Variability analysis under layout pattern-dependent Rapid-Thermal Annealing process

2009 46th ACM/IEEE Design Automation Conference

DOI

2009

Compact modeling of stress effects in scaled CMOS

International Conference on Simulation of Semiconductor Processes and Devices

DOI

2009

Modeling and simulation of transistor performance shift under pattern-dependent RTA process

Advanced Lithography

DOI

2009

A framework for estimating NBTI degradation of microarchitectural components

Asia and South Pacific Design Automation Conference

DOI

2009

The Predictive Technology Model in the Late Silicon Era and Beyond

Foundations and Trends® in Electronic Design Automation

DOI

2009

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

IEEE Transactions on Electron Devices

DOI

2009

Mask-LMC: lithographic simulation and defect detection from high-resolution mask images

Photomask Japan

DOI

2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

IEEE International Symposium on Quality Electronic Design

DOI

2009

Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design

IEEE Design & Test of Computers

DOI

2009

Modeling of layout-dependent stress effect in CMOS design

IEEE/ACM International Conference on Computer-Aided Design

DOI

2009

Enabling resonant clock distribution with scaled on-chip magnetic inductors

2009 IEEE International Conference on Computer Design

DOI

2009

Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2009

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage

International Symposium on Low Power Electronics and Design

DOI

2009

Circuit aging prediction for low-power operation

IEEE Custom Integrated Circuits Conference

DOI

2009

4-NM AlN BARRIER ALL BINARY HFET WITH SiNx GATE DIELECTRIC

DOI

2009

Compact Model of Carbon Nanotube Transistor and Interconnect

IEEE Transactions on Electron Devices

DOI

2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components

International journal of parallel programming

DOI

2009

Gate replacement techniques for simultaneous leakage and aging optimization

2009 Design, Automation & Test in Europe Conference & Exhibition

DOI

2009

Top-down AlN/GaN enhancement- & depletion-mode nanoribbon HEMTs

Device Research Conference

DOI

2009

Defect printability analysis by lithographic simulation from high resolution mask images

Photomask Technology

DOI

2008

Understanding illumination effects for control of optical proximity effects (OPE)

SPIE Advanced Lithography

DOI

2008

Scalable model for predicting the effect of negative bias temperature instability for reliable design

IET Circuits Devices Syst.

DOI

2008

Reliable Systems on Unreliable Fabrics

IEEE Design & Test of Computers

DOI

2008

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

2008 45th ACM/IEEE Design Automation Conference

DOI

2008

Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations

IEEE International Symposium on Quality Electronic Design

DOI

2008

2.3 nm barrier AlN/GaN HEMTs with insulated gates

DOI

2008

Optimized Circuit Failure Prediction for Aging: Practicality and Promise

2008 IEEE International Test Conference

DOI

2008

Formation of ohmic contacts to ultra-thin channel AlN/GaN HEMTs

DOI

2008

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design

IEEE International Symposium on Quality Electronic Design

DOI

2008

Design rule optimization of regular layout for leakage reduction in nanoscale design

Asia and South Pacific Design Automation Conference

DOI

2008

Development of a computational lithography roadmap

SPIE Advanced Lithography

DOI

2008

Methods and System for Lithography Process Simulation Window.

2008

Statistical prediction of NBTI-induced circuit aging

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

DOI

2008

Finite-Point Gate Model for Fast Timing and Power Analysis

IEEE International Symposium on Quality Electronic Design

DOI

2008

Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect

IEEE International Symposium on Quality Electronic Design

DOI

2008

Statistical prediction of circuit aging under process variations

IEEE Custom Integrated Circuits Conference

DOI

2008

AlN/GaN Insulated-Gate HEMTs With 2.3 A/mm Output Current and 480 mS/mm Transconductance

IEEE Electron Device Letters

DOI

2007

Compact Modeling of a PD SOI MESFET for Wide Temperature Designs

IEEE International Symposium on Quality Electronic Design

DOI

2007

Extraction and Modeling of Process Variations for Robust Nanoscale Design

2007

Compact modeling of carbon nanotube transistor for early stage process-design exploration

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

DOI

2007

Infrared reflectivity spectroscopy of optical phonons in short-period AlGaN/GaN superlattices

SPIE NanoScience + Engineering

DOI

2007

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

IEEE Custom Integrated Circuits Conference

DOI

2007

A New Simulation Method for NBTI Analysis in SPICE Environment

IEEE International Symposium on Quality Electronic Design

DOI

2007

Session details: Silicon measurement correlation to reliability, noise and timing effects

Design Automation Conference

DOI

2007

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

IEEE transactions on device and materials reliability

DOI

2007

MOSFET Modeling for 45nm and Beyond

IEEE/ACM International Conference on Computer-Aided Design

DOI

2007

MBE-Grown Ultrashallow AlN/GaN HEMT Technology

DOI

2007

MBE-Grown Ultra-shallow AlN/GaN HFET Technology

DOI

2007

A robust finite-point based gate model considering process variations

IEEE/ACM International Conference on Computer-Aided Design

DOI

2007

Optimizing finfet technology for high-speed and low-power design

ACM Great Lakes Symposium on VLSI

DOI

2007

Rigorous extraction of process variations for 65nm CMOS design

European Solid-State Device Research Conference

DOI

2007

Predictive technology modeling for 32nm low power design

International Semiconductor Device Research Symposium

DOI

2007

Fast and accurate 3D mask model for full-chip OPC and verification

SPIE Advanced Lithography

DOI

2007

The Impact of NBTI on the Performance of Combinational and Sequential Circuits

2007 44th ACM/IEEE Design Automation Conference

DOI

2007

An efficient method to identify critical gates under circuit aging

IEEE/ACM International Conference on Computer-Aided Design

DOI

2007

Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model

2007 Design, Automation & Test in Europe Conference & Exhibition

DOI

2007

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation

2007 44th ACM/IEEE Design Automation Conference

DOI

2006

Modeling and minimization of PMOS NBTI effect for robust nanometer design

2006 43rd ACM/IEEE Design Automation Conference

DOI

2006

Analysis and Modeling of CD Variation for Statistical Static Timing

IEEE/ACM International Conference on Computer-Aided Design

DOI

2006

Analysis of pulse signaling for low-power on-chip global bus design

IEEE International Symposium on Quality Electronic Design

DOI

2006

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

IEEE Transactions on Electron Devices

DOI

2006

SRAM Cell Optimization for Ultra-Low Power Standby

Journal of Low Power Electronics

DOI

2006

A new analytic approximation to general diode equation

DOI

2006

High-Voltage CMOS Compatible SOI MESFET Characterization and Spice Model Extraction

IEEE MTT-S International Microwave Symposium Digest

DOI

2006

New generation of predictive technology model for sub-45nm design exploration

IEEE International Symposium on Quality Electronic Design

DOI

2006

LOTUS: leakage optimization under timing uncertainty for standard-cell designs

IEEE International Symposium on Quality Electronic Design

DOI

2006

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

2006 43rd ACM/IEEE Design Automation Conference

DOI

2006

Predictive Technology Model for Nano-CMOS Design Exploration

2006 1st International Conference on Nano-Networks and Workshops

DOI

2006

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Asia and South Pacific Conference on Design Automation, 2006.

DOI

2006

Predictive Modeling of the NBTI Effect for Reliable Design

IEEE Custom Integrated Circuits Conference

DOI

2006

Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection

Journal of Low Power Electronics

DOI

2005

Nano‐CMOS Scaling Problems and Implications

DOI

2005

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2005

Design for Manufacturability

DOI

2005

Standby supply voltage minimization for deep sub-micron SRAM

Microelectronics Journal

DOI

2005

Mapping statistical process variations toward circuit performance variability: an analytical modeling approach

Proceedings - Design Automation Conference

DOI

2005

Modeling within-die spatial correlation effects for process-design co-optimization

IEEE International Symposium on Quality Electronic Design

DOI

2005

Robust design of high fan-in/out subthreshold circuits

ICCD

DOI

2005

Modeling within-field gate length spatial variation for process-design co-optimization

SPIE Advanced Lithography

DOI

2004

SRAM leakage suppression by minimizing standby supply voltage

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

DOI

2004

Ultra-low-voltage robust design issues in deep-submicron CMOS

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.

DOI

2003

Switch-factor based loop RLC modeling for efficient timing analysis

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

DOI

2003

Compact Modeling for RF and Microwave Integrated Circuits

2003

Yield optimization with energy-delay constraints in low-power digital circuits

International Conference on Electron Devices and Solid-State Circuits

DOI

2003

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

IEEE J. Solid State Circuits

DOI

2003

Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DOI

2003

Modeling metal dishing for interconnect optimization

IEEE International Electron Devices Meeting 2003

DOI

2003

Improved a priori interconnect predictions and technology extrapolation in the GTX system

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2003

Spice up your MOSFET modelling

DOI

2002

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Proceedings of the IEEE Custom Integrated Circuits Conference

DOI

2002

Design sensitivities to variability: extrapolations and assessments in nanometer VLSI

15th Annual IEEE International ASIC/SOC Conference

DOI

2002

Efficient generation of delay change curves for noise-aware static timing analysis

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

DOI

2002

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

15th Annual IEEE International ASIC/SOC Conference

DOI

2002

Analytical performance models for RLC interconnects and application to clock optimization

15th Annual IEEE International ASIC/SOC Conference

DOI

2002

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

DOI

2002

Frequency-independent equivalent circuit model for on-chip spiral inductors

Proceedings of the IEEE Custom Integrated Circuits Conference

DOI

2001

Accurate in situ measurement of peak noise and delay change induced by interconnect coupling

IEEE J. Solid State Circuits

DOI

2000

RLC signal integrity analysis of high-speed global interconnects [CMOS]

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

DOI

2000

GTX: the MARCO GSRC technology extrapolation system

Proceedings - Design Automation Conference

DOI

2000

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Proceedings of the IEEE Custom Integrated Circuits Conference

DOI

2000

Characterization of interconnect coupling noise using in-situ delay-change curve measurements

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

DOI

2000

Effects of global interconnect optimizations on performance estimation of deep submicron design

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

DOI

2012

Multi-level reliability simulation for IC design

IEEE International Conference on Solid-State and Integrated Circuit Technology

DOI