2026

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising--Similarity for Diffusion Models

Ruiqi Guo, Lei Wang, Xiaofeng Chen, Keyi Jiang, Zhiheng Yue, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

IEEE Journal of Solid-State Circuits

DOI

2026

Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin

DOI

2025

3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration

Zhiheng Yue, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture

DOI

2025

A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices

Yuanzhe Zhao, Yang Wang, Rui Paulo Martins, Chi‐Hang Chan, Shouyi Yin, Minglei Zhang

IEEE Journal of Solid-State Circuits

DOI

2025

GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs

Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao

Proceedings - ACM IEEE Design Automation Conference

DOI

2025

CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-Based Edge LLM Accelerator with 1.78ms-Response in Prefill and 31.32 Token/s in Decoding

Zihan Wu, Yiqi Wang, Zhen He, Bohan Yang, Yang Wang, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin

DOI

2025

李金熹，尹首一，魏少军，胡杨

《计算机工程与科学》

2024

大模型芯片与系统专题简介

尹首一，唐漾，涂锋斌

《中国科学:信息科学》

2024

基于遗传算法的晶圆级芯片映射算法研究

李成冉，方佳豪，尹首一，魏少军，胡杨

《计算机工程与科学》

2024

Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin

DOI

2024

Proceedings - ACM IEEE Design Automation Conference

DOI

2021

2019

A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection

Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei

IEEE Journal of Solid-State Circuits

DOI

2019

A Multi-Task Hardwired Accelerator for Face Detection and Alignment

Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Shouyi Yin, Shaojun Wei

IEEE Transactions on Circuits and Systems for Video Technology

DOI

2019

Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation

Pan Wang, Leibo Liu, Sheng Zhou, Guiqiang Peng, Shouyi Yin, Shaojun Wei

IEEE Transactions on Wireless Communications

DOI

2019

尹首一，郭珩，魏少军

《科技导报》

2018

DOI

2016

2012

可重构计算处理器技术

魏少军，刘雷波，尹首一

《中国科学:信息科学》

2012

Hui Gao, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei

International Conference on Computing Technology and Information Management

2012

Parallelism optimization with variables affinity graph for reconfigurable computing architecture

Shizhu Liu, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei

International Conference on Computing Technology and Information Management

2012

A general configurable wireless sensor network system based on SD card

Jianfeng Chen, Shouyi Yin, Dajiang Liu, Hui Gao, Shaojun Wei

International Conference on Computing Technology and Information Management

2012

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Shaojun Wei

IEICE Transactions on Information and Systems

DOI

2012

Multi-Battery Scheduling for Battery-Powered DVS Systems

Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei

IEICE Transactions on Communications

DOI

2012

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture

Dajiang Liu, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei

IEICE Transactions on Information and Systems

DOI

2012

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC

Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu, Shaojun Wei

IEICE Transactions on Electronics

DOI

2011

Ao Luo, Shouyi Yin, Leibo Liu, Renyan Zhou, Shaojun Wei

DOI

2010

A reconfigurable multi-processor SoC for media applications

Min Zhu, Leibo Liu, Shouyi Yin, Yansheng Wang, Wenjie Wang, Shaojun Wei

DOI

2010

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Wen Jia, Shaojun Wei

DOI

2009

嵌入式粗颗粒度可重构处理器的软硬件协同设计流程

于苏东，刘雷波，尹首一，魏少军

《电子学报》

2009

可重构媒体处理器测试程序生成技术

尹首一，王晨阳，魏少军

《吉林大学学报(工学版)》

Shouyi Yin, Yongqiang Xiong, Qian Zhang, Xiaokang Lin

Wireless Communications and Mobile Computing

DOI

2006

Prediction-based routing for real time communications in wireless multi-hop networks

Shouyi Yin, Yongqiang Xiong, Qian Zhang, Xiaokang Lin

DOI

2005

Multipath minimum energy routing in ad hoc network

Shouyi Yin, Xiaokang Lin

International Conference on Communications

DOI

2005

Shouyi Yin, Xiaokang Lin

Lecture notes in computer science

DOI

精选作品

期刊论文

MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference

TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips

WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip

PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion

FACE: Fully Overlapped PD Scheduling and Multi-Level Architecture Co-Exploration on Wafer

ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips

HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction

MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference

WaferSim: A Simulation Infrastructure for LLM Service on Wafer-Scale Chips

PDAcc: A Prefill-Decode Disaggregated MCM-Based Accelerator for Multi-Task Large Language Model Applications

GFRA: A High-Utilization Grain-Fused Reconfigurable Architecture for Coarse-Grained and Fine-Grained Applications

A 28nm 44.15TFLOPS/W and 1.57TFLOPS/mm 2 Joint-Alignment Floating-Point CIM Macro with ISO26262 ASIL-D Safety Level for Autonomous Driving

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising--Similarity for Diffusion Models

Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation

A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models

2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering

A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation

BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination

MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts

LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model

An Energy-Efficient Transformer Fine-Tuning Processor for Personalized Edge Applications

An LLM Accelerator With Bidirectional Microscaling Quantization

A Valuewise Hybrid-Domain Compute-In-Memory Macro for Energy-Efficient Edge-AI Devices

A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer

PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture

AutoDSRI: An Automated Framework for Domain‐Specific Reusable Interposer Based Chiplets Design

MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration

WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips

PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer

Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction

Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling

XY-Serve: End-to-End Versatile Production Serving for Dynamic LLM Workloads

A 77.35 TOPS/W Transformer Processor Exploiting Multi-Scope Similarity in Attention Computing

RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing

Segmentation-Aware Optimization of Collective for Waferscale Chips

Spatial-Aware Orchestration of LLM Attention on Waferscale Chips

A 22nm 38.9TFLOPS/W Computing-on-BENES-Network LLM Processor with Redundant Weight-bits Elimination and Key-Value Computing Reformulation

PDAcc: A 541 Tokens/s@Llama-1.2B Effective Throughput Prefill-Decode Disaggregated MCM-based Accelerator for Multi-task Large Language Model Applications

P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture

3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration

A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices

GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs

CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-Based Edge LLM Accelerator with 1.78ms-Response in Prefill and 31.32 Token/s in Decoding

LLM-CIM: A 28nm 126.7TOPS/W Input-LUT-Based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMs

Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme

GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism

ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction

UPE: A Device-Edge DNN Inference Artificial Intelligence Processor with Supporting Reconfigurable Training

A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-30 Loss for Compound AI

23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation

BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training

An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures

BLADE: Energy‐efficient attention accelerator with fused kernel and bit‐level redundancy elimination

ACRIN: Asymmetric Compression‐Recovery Interconnection Network for Inter‐Chip Sparsity Architecture

基于MLIR的数据流模型

大模型芯片与系统专题简介

基于遗传算法的晶圆级芯片映射算法研究

基于Actor模型的众核数据流硬件架构探索

Review of chiplet-based design: system architecture and interconnection

A Lightweight 3D D2D Interface for Active Interposer Chiplet Systems

MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture

E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping

A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing

GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications

Efficient Orchestrated AI Workflows Execution on Scale-Out Spatial Architecture

Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction

Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization

GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference

FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing