向东｜清华大学｜学者主页

2026

芯粒集成芯片的测试与可测试性设计技术

丁浩宸，向东

《集成技术》

2024

逻辑内建自测试技术进展综述

金敏，向东

《集成技术》

2023

Test Compression for Launch-on-Capture Transition Fault Testing

Dong Xiang

ACM Transactions on Design Automation of Electronic Systems

DOI

2020

Deadlock‐free adaptive 3D network‐on‐chips routing algorithm with repetitive turn concept

Yuan Cai, Dong Xiang, Xiang Ji

IET Communications

DOI

2020

Connectivity and Diagnosability of Leaf-Sort Graphs

Mujiangshan Wang, Dong Xiang, Shi-Ying Wang

Parallel Processing Letters

DOI

2018

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara

ACM Transactions on Design Automation of Electronic Systems

DOI

2016

Thermal-aware small-delay defect testing in integrated circuits

Yu Bai, Dong Xiang

China Semiconductor Technology International Conference (CSTIC)

DOI

2016

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

Dong Xiang, Kele Shen

ACM Transactions on Design Automation of Electronic Systems

DOI

2015

A scan segmentation architecture for power controllability and reduction

Zhou Jiang, Dong Xiang, Kele Shen

IEEE International System-on-Chip Conference (SOCC)

DOI

2014

A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs

Dong Xiang, Kele Shen

ACM Journal on Emerging Technologies in Computing Systems

DOI

2013

基于三维芯片热驱动的扫描测试策略

神克乐，向东

《电子学报》

2013

Torus网络中基于中心距离的完全自适应路由算法

虞志刚，向东，王新玉

《电子学报》

2013

片上网络路由器及互连低成本测试方法

向东

《集成技术》

2013

VCBR: Virtual Channel Balanced Routing in Torus Networks

Zhigang Yu, Dong Xiang, Xinyu Wang

DOI

2013

A Fault-Tolerant Routing Algorithm Design for On-Chip Optical Networks

Dong Xiang, Yan Zhang, Shuchang Shan, Yi Xu

Proceedings/Proceedings - Symposium on Reliable Distributed Systems

DOI

2013

Test compaction for small-delay defects using an effective path selection scheme

Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin

ACM Transactions on Design Automation of Electronic Systems

DOI

2012

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Dong Xiang, Zhen Chen, Laung‐Terng Wang

ACM Transactions on Design Automation of Electronic Systems

DOI

2011

Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data

Dong Xiang, Zhen Chen

Proceedings - Asian Test Symposium/Proceedings

DOI

2011

Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment

Zhen Chen, Jia Li, Dong Xiang, Yu Huang

Proceedings - Asian Test Symposium/Proceedings

DOI

2011

An Efficient Adaptive Deadlock-Free Routing Algorithm for Torus Networks

Wei Luo, Dong Xiang

IEEE Transactions on Parallel and Distributed Systems

DOI

2010

MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Zhe Chen, Krishnendu Chakrabarty, Dong Xiang

DOI

2010

Low-capture-power at-speed testing using partial launch-on-capture test scheme

Zhe Chen, Dong Xiang

Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium

DOI

2010

A Unified Solution to Scan Test Volume, Time, and Power Minimization

Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya

International Conference on VLSI Design

DOI

2009

A power-effective scan architecture using scan flip-flops clustering and post-generation filling

Zhen Chen, Dong Xiang, Boxue Yin

ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI

2009

The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost

Zhen Chen, Dong Xiang, Boxue Yin

Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium

DOI

2009

A Low Power Architecture based on Unidirectional Cut

Zhen Chen, Dong Xiang

ECS Transactions

DOI

2009

Conflict driven scan chain configuration for high transition fault coverage and low test power

Zhe Chen, Boxue Yin, Dong Xiang

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2009

New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets

Boxue Yin, Dong Xiang, Zhen Chen

International Conference on VLSI Design

DOI

2008

Scan BIST with biased scan test signals

Dong Xiang, Mingjing Chen, Jiaguang Sun

Science in China Series F Information Sciences

DOI

2008

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST

Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2008

Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model

Dong Xiang, Larry Yueli Zhang, Yi Feng Pan

IEEE Transactions on Computers

DOI

2008

Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme

Dong Xiang, Yi Feng Pan, Qi Wang, Zhen Chen

IEEE International Conference on Distributed Computing Systems (ICDCS)

DOI

2008

A Density Adaptive Routing Protocol for Large-Scale Ad Hoc Networks

Zhizhou Li, Yaxiong Zhao, Yong Cui, Dong Xiang

IEEE Wireless Communications and Networking Conference

DOI

2007

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

Dong Xiang, Mingjing Chen, Hideo Fujiwara

IEEE Transactions on Computers

DOI

2007

Deadlock-Free Adaptive Routing in Meshes Based on Cost-Effective Deadlock Avoidance Schemes

Dong Xiang, Larry Yueli Zhang, Yi Feng Pan, Jie Wu

Proceedings of the International Conference on Parallel Processing

DOI

2007

Routing Protocol Based on Multiple Dominating Set in Ad hoc Networks

Dong Xiang

Jisuanji yingyong yanjiu

2007

Clock-disabling scheme to reduce test power

Dong Xiang

Journal of Tsinghua University(Science and Technology)

2006

采用加权选通信号的扫描自测试方法

向东，陈明静，孙家广

《中国科学:技术科学》

2006

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture

Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Jiaguang Sun, Hideo Fujiwara

DOI

2005

基于扫描森林的BIST策略

陈明静，向东

《计算机工程与科学》

2005

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops

Dong Xiang, Kai Li, Hideo Fujiwara

Proceedings - Asian Test Symposium/Proceedings

DOI

2004

采用独立复位信号的同步时序电路可测试性设计

向东，顾珊，徐奕

《计算机学报》

2003

Improving test quality of scan-based BIST by scan chain partitioning

Dong Xiang, Mingjing Chen, Jiaguang Sun, Fujiwara

DOI

2003

A cost-effective scan architecture for scan testing with non-scan test power and test application cost

Dong Xiang, Shan Gu, Jiaguang Sun, Yu‐Liang Wu

Proceedings - ACM IEEE Design Automation Conference

DOI

2002

Non-scan design for testability for synchronous sequential circuits based on conflict analysis

Dong Xiang, Yi Xu, H. Fijiwara

Proceedings/Proceedings - International Test Conference

DOI

2000

Reliable Unicasting in Faulty Hypercube Multicomputers Based on Local Safety Information

Dong Xiang, Jie Wu

DOI

1999

并行测试的一种新策略——测试段划分

向东

《电子学报》

1997

数字系统测试及可测试性设计

向东

1993

并行测试的测试调度及其控制

向东，魏道政

《电子学报》

1992

分布式系统中的动态测试调度

向东，魏道政

《电子学报》

1991

一种基于知识的可测试性设计

向东

《电子学报》

精选作品

期刊论文

芯粒集成芯片的测试与可测试性设计技术

逻辑内建自测试技术进展综述

Test Compression for Launch-on-Capture Transition Fault Testing

Deadlock‐free adaptive 3D network‐on‐chips routing algorithm with repetitive turn concept

Connectivity and Diagnosability of Leaf-Sort Graphs

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

Thermal-aware small-delay defect testing in integrated circuits

A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing

A scan segmentation architecture for power controllability and reduction

A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs

基于三维芯片热驱动的扫描测试策略

Torus网络中基于中心距离的完全自适应路由算法

片上网络路由器及互连低成本测试方法

VCBR: Virtual Channel Balanced Routing in Torus Networks

A Fault-Tolerant Routing Algorithm Design for On-Chip Optical Networks

Test compaction for small-delay defects using an effective path selection scheme

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data

Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment

An Efficient Adaptive Deadlock-Free Routing Algorithm for Torus Networks

MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Low-capture-power at-speed testing using partial launch-on-capture test scheme

A Unified Solution to Scan Test Volume, Time, and Power Minimization

A power-effective scan architecture using scan flip-flops clustering and post-generation filling

The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost

A Low Power Architecture based on Unidirectional Cut

Conflict driven scan chain configuration for high transition fault coverage and low test power

New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets

Scan BIST with biased scan test signals

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST

Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model

Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme

A Density Adaptive Routing Protocol for Large-Scale Ad Hoc Networks

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

Deadlock-Free Adaptive Routing in Meshes Based on Cost-Effective Deadlock Avoidance Schemes

Routing Protocol Based on Multiple Dominating Set in Ad hoc Networks

Clock-disabling scheme to reduce test power

采用加权选通信号的扫描自测试方法

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture

基于扫描森林的BIST策略

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops

采用独立复位信号的同步时序电路可测试性设计

Improving test quality of scan-based BIST by scan chain partitioning

A cost-effective scan architecture for scan testing with non-scan test power and test application cost

Non-scan design for testability for synchronous sequential circuits based on conflict analysis

Reliable Unicasting in Faulty Hypercube Multicomputers Based on Local Safety Information

并行测试的一种新策略——测试段划分

数字系统测试及可测试性设计

并行测试的测试调度及其控制

分布式系统中的动态测试调度

一种基于知识的可测试性设计

会议论文

细粒度无死锁路由算法Opt-DP下二维NoC路由器内部机制

基于扫描森林的BIST策略:一种新的可测试性设计方法

基于局部故障块的3维mesh／torus网的容错路由

研究方向