周强

2023

Global Routing Under a Congestion-Aware Reinforcement Learning Model

International Symposium of Electronics Design Automation (ISEDA)

DOI

2023

Static Probability Analysis Guided RTL Hardware Trojan Test Generation

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI

2022

通过电源完整性分析和电迁移修复提高供电网络可靠性

《计算机辅助设计与图形学学报》

2022

Intelligent and kernelized placement: A survey

Integration

DOI

2022

A survey on machine learning-based routing for VLSI physical design

Integration

DOI

2021

A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model

International Symposium on Circuits and Systems

DOI

2021

An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network

International Symposium on Circuits and Systems

DOI

2021

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2021

Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks

Journal of Computer Science and Technology

DOI

2021

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs

DOI

2021

DrPlace: A Deep Learning Based Routability-Driven VLSI Placement Algorithm

Journal of Computer-Aided Design & Computer Graphics

DOI

2020

A game theory approach for RTL security verification resources allocation

CCF Transactions on High Performance Computing

DOI

2019

Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding

Integr.

DOI

2019

Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2019

A high-level information flow tracking method for detecting information leakage

Integr.

DOI

2019

Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks

International Symposium on Circuits and Systems

DOI

2018

HLIFT: A high-level information flow tracking method for detecting hardware Trojans

Asia and South Pacific Design Automation Conference

DOI

2018

Spear and Shield: Evolution of Integrated Circuit Camouflaging

Journal of Computational Science and Technology

DOI

2018

ASAX: Automatic security assertion extraction for detecting Hardware Trojans

Asia and South Pacific Design Automation Conference

DOI

2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2018

Electromigration Design Rule aware Global and Detailed Routing Algorithm

ACM Great Lakes Symposium on VLSI

DOI

2018

Electromagnetic Equalizer: An Active Countermeasure Against EM Side-channel Attack

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2018

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks

Asia and South Pacific Design Automation Conference

DOI

2018

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit

Journal of Computational Science and Technology

DOI

2018

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2017

Cell spreading optimization for force-directed global placers

International Symposium on Circuits and Systems

DOI

2017

An Effective Power Grid Optimization Approach for the Electromigration Reliability

IEEE Computer Society Annual Symposium on VLSI

DOI

2017

Gate Camouflaging-Based Obfuscation

DOI

2017

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack

ACM Great Lakes Symposium on VLSI

DOI

2017

Crossover Ring Oscillator PUF

IEEE International Symposium on Quality Electronic Design

DOI

2017

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack

ICCD

DOI

2017

Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans

ICCD

DOI

2016

考虑设计规则的引脚分配算法

《计算机辅助设计与图形学学报》

2016

マルチプレクサを用いた安全かつ低オーバヘッド回路難読化技術【Powered by NICT】

2016

An efficient framework for configurable RO PUF

International Symposium on Circuits and Systems

DOI

2016

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

Journal of Computational Science and Technology

DOI

2016

Is the Secure IC camouflaging really secure?

International Symposium on Circuits and Systems

DOI

2016

MCFRoute 2.0: A redundant via insertion enhanced concurrent detailed router

ACM Great Lakes Symposium on VLSI

DOI

2016

Secure and low-overhead circuit obfuscation technique with multiplexers

ACM Great Lakes Symposium on VLSI

DOI

2015

An efficient buffer sizing algorithm for clock trees considering process variations

Asia Symposium on Quality Electronic Design

DOI

2015

Register Clustering Methodology for Low Power Clock Tree Synthesis

Journal of Computational Science and Technology

DOI

2015

An accurate detailed routing routability prediction model in placement

Asia Symposium on Quality Electronic Design

DOI

2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2015

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths

Journal of Computational Science and Technology

DOI

2015

Fast synthesis of low power clock trees based on register clustering

Sixteenth International Symposium on Quality Electronic Design

DOI

2015

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators

International Conference on Computer-Aided Design and Computer Graphics

DOI

2015

A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2015

SIAR: Customized real-time interactive router for analog circuits

Integr.

DOI

2015

3-D global routing with layer directive and scenic constraints

Asia Symposium on Quality Electronic Design

DOI

2014

矩形Steiner最小树布线灵活度

《计算机辅助设计与图形学学报》

2014

Flexibility in Rectilinear Steiner Minimal Tree

DOI

2014

Trusted Integrated Circuits: The Problem and Challenges

Journal of Computational Science and Technology

DOI

2014

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2014

Accurate prediction of detailed routing congestion using supervised data learning

ICCD

DOI

2014

Power supply noise aware evaluation framework for side channel attacks and countermeasures

International Conference on Field-Programmable Technology

DOI

2014

VFGR: A very fast parallel global router with accurate congestion modeling

Asia and South Pacific Design Automation Conference

DOI

2014

A register clustering algorithm for low power clock tree synthesis

International Symposium on Circuits and Systems

DOI

2014

RSMT construction algorithm based on Congestion-Oriented Flexibility

IEEE Latin American Symposium on Circuits and Systems

DOI

2014

Length matching in detailed routing for analog and mixed signal circuits

Microelectronics Journal

DOI

2014

An effective iterative density aware detailed placement algorithm

International Symposium on Circuits and Systems

DOI

2014

PowerRush: An Efficient Simulator for Static Power Grid Analysis

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2014

MCFRoute: A detailed router based on multi-commodity flow method

DOI

2014

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs

Journal of Computer Science and Technology

DOI

2013

应用于大规模ASIC的线长驱动的合法化算法

《计算机科学》

2013

应用于大规模集成电路非线性布局的二元结群算法

《计算机辅助设计与图形学学报》

2013

Selected inversion for vectorless power grid verification by exploiting locality

ICCD

DOI

2013

Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model

International Conference on Computer-Aided Design and Computer Graphics

DOI

2013

A Steiner tree construction method for flexibility and congestion optimization

International Conference on Communications, Circuits and Systems

DOI

2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection

International Conference on Computer-Aided Design and Computer Graphics

DOI

2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

DOI

2013

A new splitting graph construction algorithm for SIAR router

2013 IEEE 10th International Conference on ASIC

DOI

2013

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs

Integr.

DOI

2013

Wire-length Driven Legalization Algorithm for Large-scale ASIC

2013

Chip layer assignment method for analytical placement of 3D ICs

International Conference on Communications, Circuits and Systems

DOI

2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function

International Conference on Field-Programmable Logic and Applications

DOI

2013

GPCS: Global placement based on cell spreading method

International Conference on Communications, Circuits and Systems

DOI

2013

An effective legalization approach based on multiple ordering

International Conference on Communications, Circuits and Systems

DOI

2013

Design and implementation of a group-based RO PUF

Design, Automation and Test in Europe

DOI

2013

Analog routing considering min-area constraint

2013 IEEE 10th International Conference on ASIC

DOI

2012

一种基于敏感度的时延驱动快速布局算法

《电子学报》

2012

PowerRush : Efficient transient simulation for power grid analysis

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2012

Accurate and fast cell spreading for force directed placement

Asia Symposium on Quality Electronic Design

DOI

2012

A DyadicCluster method used for nonlinear placement

IEEE International Symposium on Quality Electronic Design

DOI

2012

Thermal-aware power network design for IR drop reduction in 3D ICs

Asia and South Pacific Design Automation Conference

DOI

2012

TimFastPlace: Critical-path based timing driven FastPlace

IEICE Electronics Express

DOI

2011

一种利用图建模的宏模块合法化算法

《小型微型计算机系统》

2011

基于FastPlace总体布局算法的实现

《小型微型计算机系统》

2011

应用于大规模FPGA的解析式布局算法

《计算机辅助设计与图形学学报》

2011

TIPO: A heuristic algorithm for delay constrained power optimization

2011 International Conference on Consumer Electronics, Communications and Networks (CECNet)

DOI

2011

A novel fine-grain track routing approach for routability and crosstalk optimization

IEEE International Symposium on Quality Electronic Design

DOI

2011

Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2011

A fast recursive detailed routing algorithm for hierarchical FPGAs

International Conference on Computer Supported Cooperative Work in Design

DOI

2011

Partition-Based Global Placement Considering Wire-Density Uniformity for CMP Variations

DOI

2011

A timing-perspective study on the wire model in placement

2011 9th IEEE International Conference on ASIC

DOI

2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

ACM Great Lakes Symposium on VLSI

DOI

2011

Markov Clustering-Based Placement Algorithm for Hierarchical FPGAs

Tsinghua Science and Technology

2011

PowerRush: A linear simulator for power grid

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2011

SIAR: splitting-graph-based interactive analog router

ACM Great Lakes Symposium on VLSI

DOI

2011

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits

IEEE International Symposium on Quality Electronic Design

DOI

2011

Implementation of Global Placement Based on FastPlace Algorithm

2011

A fast placement and global routing integrated algorithm for hierarchical FPGAs

International Conference on Information and Software Technologies

DOI

2011

Markov Clustering-Based Placement Algorithm for Hierarchical FPGAs * * Supported by the National Natural Science Foundation of China (No. 60833004)

DOI

2011

Fast poisson solver preconditioned method for robust power grid analysis

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2011

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment

IEEE Computer Society Annual Symposium on VLSI

DOI

2010

考虑重叠度和线长的单元密度平滑方法

《计算机辅助设计与图形学学报》

2010

针对宏模块的合法化技术

《计算机科学》

2010

基于线性规划的最小扰动标准单元合法化算法

《微电子学》

2010

基于整数规划的层次式FPGA布线算法

《计算机辅助设计与图形学学报》

2010

预先指定单元位置的时延驱动布局优化方法

《计算机辅助设计与图形学学报》

2010

层次式FPGA快速可布性布线算法

《计算机辅助设计与图形学学报》

2010

层次式FPGA快速布局算法

《计算机辅助设计与图形学学报》

2010

Legalization Algorithm for Macro Problems

2010

Satisfiability problem-based manufacturable hot spot disconnecting and rerouting method

2010

Thermal Impacts of Leakage Power in 2D/3D floorplanning

J. Circuits Syst. Comput.

DOI

2010

A low power clock network placement framework

IEEE International Symposium on Quality Electronic Design

DOI

2010

An effective detailed placement algorithm for large-scale mix-mode IC design

International Conference on Future Computer and Communication

DOI

2010

A reliable detail placement tool for mixed mode IC design

International Conference on Computer Engineering and Technology

DOI

2010

A nonlinear placement technique for FPGA-like uniform granularity problem

2010 International Conference On Computer Design and Applications

DOI

2010

A fast rectangular spreading technique in global placement

International Conference on Future Computer and Communication

DOI

2010

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA

International Conference on Computer Supported Cooperative Work in Design

DOI

2010

Peak current reduction by simultaneous state replication and re-encoding

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

DOI

2010

Useful clock skew optimization under a multi-corner multi-mode design framework

IEEE International Symposium on Quality Electronic Design

DOI

2010

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

Journal of Computational Science and Technology

DOI

2010

Behavioral level dual-vth design for reduced leakage power with thermal awareness

Design, Automation and Test in Europe

DOI

2010

Markov clustering based placement algorithm for island-style FPGAs

International Conference on Green Circuits and Systems

DOI

2010

A Fast Routability-Driven Router for Hierarchical FPGA: A Fast Routability-Driven Router for Hierarchical FPGA

DOI

2010

A Design of Embedding Rewiring into Routing for FPGA Improvement

International Conference on Information Science and Applications

DOI

2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal

Design, Automation and Test in Europe

DOI

2010

A parasitic extraction method of VLSI interconnects for pre-route timing analysis

International Conference on Communications, Circuits and Systems

DOI

2010

Density Smoothing Method Considering Wire-Length and Overlap: Density Smoothing Method Considering Wire-Length and Overlap

DOI

2010

ECP- and CMP-Aware Detailed Routing Algorithm for DFM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2009

基于VPR的层次式FPGA结构描述方法研究

《微电子学》

2009

线长驱动的层次式FPGA布局算法

《微电子学》

2009

Fast congestion-aware timing-driven placement for island FPGA

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

DOI

2009

Efficient hierarchical algorithm for mixed mode placement in three dimensional integrated circuit chip designs

DOI

2009

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Integr.

DOI

2009

Cell shifting aware of wirelength and overlap

IEEE International Symposium on Quality Electronic Design

DOI

2009

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources

Asia and South Pacific Design Automation Conference

DOI

2009

An MTCMOS technology for low-power physical design

Integr.

DOI

2009

Decoupling capacitance efficient placement for reducing transient power supply noise

IEEE/ACM International Conference on Computer-Aided Design

DOI

2009

Improve clock gating through power-optimal enable function selection

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

DOI

2009

Thermal via planning aware force-directed floorplanning for D ICs

2009 IEEE 8th International Conference on ASIC

DOI

2009

A thermal-driven force-directed floorplanning algorithm for 3D ICs

2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics

DOI

2009

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2009

A fast routability-driven router for Hierarchical FPGAs based on Tabu search

International Conference on Communications, Circuits and Systems

DOI

2009

A detailed router for hierarchical FPGAs based on simulated evolution

International Symposium on VLSI Design, Automation and Test

DOI

2009

Global density smoothing technique for analytical placement algorithm

2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics

DOI

2009

Power optimization through edge reduction in LUT-based FPGA technology mapping

International Conference on Communications, Circuits and Systems

DOI

2009

Information hiding for trusted system design

2009 46th ACM/IEEE Design Automation Conference

DOI

2009

Fast placement for large-scale hierarchical FPGAs

2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics

DOI

2009

Wirelength Optimization for Multilevel Hierachical FPGA

WRI World Congress on Software Engineering

DOI

2008

采用统一建模的拥挤度驱动三维芯片布局算法

《计算机辅助设计与图形学学报》

2008

A novel performance driven power gating based on distributed sleep transistor network

ACM Great Lakes Symposium on VLSI

DOI

2008

Area & delay driven binding algorithm of RTL tech. mapping for heterogeneous FPGAs

International Conference on Communications, Circuits and Systems

DOI

2008

Wire density driven top-down global placement for CMP variation control

Asia Pacific Conference on Circuits and Systems

DOI

2008

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm

IEEE International Symposium on Quality Electronic Design

DOI

2008

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2008

Incremental Placement-Based Clock Network Minimization Methodology

DOI

2008

Hypergraph partitioning satisfying dual constraints on vertex and edge weight

Midwest Symposium on Circuits and Systems

DOI

2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design

Asia and South Pacific Design Automation Conference

DOI

2008

Sleep transistor sizing for multi-threshold-voltage network using Lagrange SOR iteration

Midwest Symposium on Circuits and Systems

DOI

2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation

International Conference on Field-Programmable Logic and Applications

DOI

2008

Application of optical proximity correction technology

Science in China Series F Information Sciences

DOI

2008

Cluster-based Placement for multilevel hierarchical FPGA

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

DOI

2008

DFM Based Detailed Routing Algorithm for ECP and CMP

IEEE International Symposium on Quality Electronic Design

DOI

2008

Multilevel Based Global Routing Algorithm for Hierarchical FPGA

DOI

2008

Exploiting thermal-area tradeoffs in high-level synthesis through resources number selection

International Conference on Communications, Circuits and Systems

DOI

2007

结合垂直通孔分配的层次式三维混合布局算法

《计算机辅助设计与图形学学报》

2007

高层次综合中基于整数线性规划模型的多目标功耗优化算法

《计算机辅助设计与图形学学报》

2007

高层次综合中面向功耗优化的方法与技术

《计算机辅助设计与图形学学报》

2007

交替型暗域相移掩模的并行算法

《微电子学》

2007

Logic and Layout Aware Voltage Island Generation for Low Power Design

Asia and South Pacific Design Automation Conference

DOI

2007

A Yield-Driven Gridless Router

Journal of Computational Science and Technology

DOI

2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2007

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement

2007 IEEE International Symposium on Circuits and Systems

DOI

2007

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan

IEEE Computer Society Annual Symposium on VLSI

DOI

2007

A Novel Incremental Floorplan Algorithm for Duplication in Integration of High-level Synthesis and Floorplan

International Conference on Communications, Circuits and Systems

DOI

2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

2007 IEEE International Symposium on Circuits and Systems

DOI

2007

光学近接効果補正(OPC)技術とその応用【JST・京大機械翻訳】

2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning

2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics

DOI

2007

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR

2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics

DOI

2007

A thermal-aware ILP-based algorithm in behavioral synthesis

International Conference on ASIC

DOI

2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits

IEEE/ACM International Conference on Computer-Aided Design

DOI

2007

FIDER: A force-balance-based interconnect delay driven re-synthesis algorithm for data-path optimization after floorplan

DOI

2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning

Asia and South Pacific Design Automation Conference

DOI

2007

New timing and routability driven placement algorithms for FPGA synthesis

ACM Great Lakes Symposium on VLSI

DOI

2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos

Asia and South Pacific Design Automation Conference

DOI

2007

Detailed Routing Algorithm with Optical Proximity Effects Constraint

2007

Power Delivery Aware Floorplanning for Voltage Island Designs

IEEE International Symposium on Quality Electronic Design

DOI

2007

An efficient quadratic placement based on search space traversing technology

Integr.

DOI

2007

Voltage Island Generation in Cell Based Dual-Vdd Design

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2006

带有引线端预处理的区域布线算法

《计算机辅助设计与图形学学报》

2006

高层次综合和布图规划相结合的解空间分析

《计算机辅助设计与图形学学报》

2006

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

TODE

DOI

2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials

Asia Pacific Conference on Circuits and Systems

DOI

2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment

IEEE Transactions on Circuits and Systems - II - Express Briefs

DOI

2006

A Thermal-Driven Force-Directed Macro Cell Placement Algorithm

International Conference on Communications, Circuits and Systems

DOI

2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

IEEE Transactions on Circuits and Systems Part 1: Regular Papers

DOI

2006

A Self-Adapting Multi-Kernel Controllers Generating and Placing Method for Short System Cycle

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

DOI

2006

Steiner Tree Based Routing Algorithm in Consideration of Optical Proximity Correction

International Conference on Communications, Circuits and Systems

DOI

2006

Interval Valued Variational Analysis Using the Arithmetic of Higher Order Polynomial

International Conference on Communications, Circuits and Systems

DOI

2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm

ACM International Symposium on Physical Design

DOI

2006

Congestion-Driven Placement Improvement Using Cell Spreading

International Conference on Communications, Circuits and Systems

DOI

2006

A novel technique integrating buffer insertion into timing driven placement

2006 IEEE International Symposium on Circuits and Systems

DOI

2006

Priority-Based Routing Resource Assignment Considering Crosstalk

Journal of Computational Science and Technology

DOI

2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd designs

Asia and South Pacific Conference on Design Automation, 2006.

DOI

2006

A novel low-power physical design methodology for MTCMOS

2006 IEEE International Symposium on Circuits and Systems

DOI

2006

Interconnect Power Optimization Based on the Integration of High-level Synthesis and Floorplanning

International Conference on Communications, Circuits and Systems

DOI

2006

Multilevel Routing With Redundant Via Insertion

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

DOI

2005

物理设计EDA中可扩展数据支撑系统结构

《计算机辅助设计与图形学学报》

2005

采用分层设计机制的布图系统集成

《计算机辅助设计与图形学学报》

2005

基于角模块布图表示的增量式布图规划算法(英文)

Journal of Semiconductors

2005

Crosstalk and Congestion Driven Layer Assignment Algorithm

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2005

Crosstalk-Aware Routing Resource Assignment

Journal of Computational Science and Technology

DOI

2005

Navigating registers in placement for clock network minimization

Proceedings - Design Automation Conference

DOI

2005

Clock network minimization methodology based on incremental placement

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

DOI

2005

Worst-case clock delay simulation under PG variation using gradient projection method

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005.

DOI

2005

Considering The ffect Of Standard Cell Placement In Mi ed-Size Placement

International Conference on ASIC

DOI

2005

Congestion driven incremental placement algorithm based on network flow

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005.

DOI

2005

Via assignment algorithm for hierarchical 3D placement

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005.

DOI

2005

Analysis of buffered hybrid structured clock networks

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

DOI

2005

Congestion and performance driven full-chip scalable routing framework

International Conference on ASIC

DOI

2005

Register placement for low power clock network

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

DOI

2005

Integrated routing resource assignment for RLC crosstalk minimization

2005 IEEE International Symposium on Circuits and Systems

DOI

2005

A Fast Delay Computation for the Hybrid Structured Clock Network

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

DOI

2005

Minimum error based affine arithmetic for variational timing analysis

International Conference on ASIC

DOI

2005

A new algorithm for layout of dark field alternating phase shifting masks

ACM Great Lakes Symposium on VLSI

DOI

2005

FSM decomposition for power gating design automation in sequential circuits

International Conference on ASIC

DOI

2005

3D placement algorithm with vertical via count constraints

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005.

DOI

2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design

International Conference on Embedded Software and Systems

DOI

2005

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design

Communication Systems and Applications

DOI

2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation

2005 IEEE International Symposium on Circuits and Systems

DOI

2005

Improved multilevel routing with redundant via placement for yield and reliability

ACM Great Lakes Symposium on VLSI

DOI

2005

Using CPLD to Realize Encryption Design of Secure and Credible FPGA

2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design

International Workshop on Power and Timing Modeling, Optimization and Simulation

DOI

2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem

International Conference on Computing, Networking and Communications

DOI

2004

VLSI布图中基于XML中间数据源的数据表示

《计算机工程与应用》

2004

拥挤度驱动的总体布线层分配算法

《计算机辅助设计与图形学学报》

2004

Algorithm for post global routing RLC crosstalk avoidance

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004.

DOI

2004

Layer assignment algorithm for RLC crosstalk minimization

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

DOI

2004

XML-based middle data denotation and analysis in physical design

International Conference on Communications, Circuits and Systems

DOI

2004

A fast delay analysis algorithm for the hybrid structured clock network

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

DOI

2004

A practical and efficient integrated system for VLSI/ULSI physical design

International Conference on Communications, Circuits and Systems

DOI

2004

Crosstalk driven routing resource assignment

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

DOI

2004

Building block layout by parallel simulated annealing algorithms

International Conference on Communications, Circuits and Systems

DOI

2004

Shielding Area Optimization Under the Solution of Interconnect Crosstalk

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

DOI

2003

PhyD-XML:VLSI物理设计数据标记语言设计与实现

《计算机辅助设计与图形学学报》

2003

Data-Path布图系统的数据管理

《微电子学》

2003

Effective algorithm for optimal initial solution in mixed-mode detailed placement

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2003

Cross point assignment algorithm with crosstalk constraint

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2003

A multi-layer area routing algorithm with optimized pin mapping strategy

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2003

Path-based timing optimization by buffer insertion with accurate delay model

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2003

Signal flow driven analog IC router

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2003

Congestion based layer assignment of global routing

ASIC, 2003. Proceedings. 5th International Conference on

DOI

2002

Data-path layout design inside SOC

IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions

DOI

2005

A datapath routing algorithm using bit regularity extraction

International Conference on ASIC

DOI

2005

3D placement algorithm considering vertical channels and guided by 2D placement solution

International Conference on ASIC

DOI

2005

A research on optimum-searching quadratic optimization for very large-scale standard cell placement

International Conference on ASIC

DOI

2005

A fast and stable force-directed placement with implicit buffer planning

International Conference on ASIC

DOI

2005

A shortest-path-search algorithm with symmetric constraints for analog circuit routing

International Conference on ASIC

DOI

2005

Design tools for 3D mixed mode placement

International Conference on ASIC

DOI