丁浩｜广西师范大学｜学者主页

期刊论文

2026

A two-stage optimization framework for neuron grouping and mapping in NoC-based DNN accelerators

Hao Ding, Zhengxun Wen, Xuesong Wang, Junyan Qian

The Journal of Supercomputing

DOI

2026

System-Level Fault-Tolerant Reconfiguration of 3-D VLSI Processor Arrays Under Multicomponent Failures

Hao Ding, Xiangyong Wang, Yang Xu, Junyan Qian

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

An efficient two-stage fault-balanced topology reconfiguration framework for multiprocessor arrays

Shujian Chen, Hao Ding, Yikun Yang, Junyan Qian

Journal of Systems Architecture

DOI

2025

Efficient Shortest Path-Driven Tabu Search Reconfiguration Algorithm for Multiprocessor Array

Hao Ding, Yupeng Chi, Zheng Wu, Junyan Qian, Shuxiang Song

IEEE Transactions on Dependable and Secure Computing

DOI

2025

Efficient Topology Reconfiguration Algorithm for Multiprocessor Arrays Driven by Clustered Faults

Junyan Qian, Xuming Huang, Shuo Cui, Hao Ding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2025

A Two-Stage Degradation-Based Topology Reconfiguration Algorithm for Fault-Tolerant Multiprocessor Arrays

Hao Ding, Peiling Song, Yelin Li, Junyan Qian

ACM Transactions on Architecture and Code Optimization

DOI

2024

基于0.18μm CMOS工艺的低功耗采样保持电路

韩昌霖，丁浩，吴建飞

《微电子学》

2024

一种无回跳特性TVS的快速建模方法及验证

韩昌霖，吴建飞，郑亦菲，陈乐东，丁浩

《现代电子技术》

2024

Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm

Junyan Qian, Chuanfang Zhang, Zheng Wu, Hao Ding, Long Li

Journal of Parallel and Distributed Computing

DOI

2023

An Efficient Bottleneck Planes Exclusion Method for Reconfiguring 3D VLSI Arrays

Junyan Qian, Kunzhu Qiu, Hao Ding, Huimin Zhang, Zhongyi Zhai

IEEE Transactions on Parallel and Distributed Systems

DOI

2023

Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect

Hao Ding, Yanlong He, Zhongyi Zhai, Zhi Li, Junyan Qian, Lingzhong Zhao

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2022

面向Mesh网络的容错处理器阵列重构方法研究

丁浩

《桂林电子科技大学》

2021

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

Hao Ding, Junyan Qian, Lingzhong Zhao, Zhongyi Zhai

Journal of Parallel and Distributed Computing

DOI

2021

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Hao Ding, Junyan Qian, Lingzhong Zhao, Zhongyi Zhai

Integration

DOI

2021

An improved algorithm for accelerating reconfiguration of VLSI array

Junyan Qian, Fuhao Mo, Hao Ding, Zhide Zhou, Lingzhong Zhao, Zhongyi Zhai

Integration

DOI

2021

Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting

Hao Ding, Junyan Qian, Bisheng Huang, Lingzhong Zhao, Zhongyi Zhai

Journal of Parallel and Distributed Computing

DOI

预印本

2026

HEMERA: A Heterogeneous Memory-Centric Accelerator with Recursive Dataflow for Edge-Constrained State-Space-Duality Models Inference

Hao Ding, Ling Liang, Ruitong Qiao, Dongxue Zhao, Xiantong Qiu, Jinshan Li, Meng Li, Lei Jin, Zhiliang Xia, Zongliang Huo, Zongwei Wang, Yimao Cai

arXiv preprint

丁浩

精选作品

期刊论文

A two-stage optimization framework for neuron grouping and mapping in NoC-based DNN accelerators

System-Level Fault-Tolerant Reconfiguration of 3-D VLSI Processor Arrays Under Multicomponent Failures

An efficient two-stage fault-balanced topology reconfiguration framework for multiprocessor arrays

Efficient Shortest Path-Driven Tabu Search Reconfiguration Algorithm for Multiprocessor Array

Efficient Topology Reconfiguration Algorithm for Multiprocessor Arrays Driven by Clustered Faults

A Two-Stage Degradation-Based Topology Reconfiguration Algorithm for Fault-Tolerant Multiprocessor Arrays

基于0.18μm CMOS工艺的低功耗采样保持电路

一种无回跳特性TVS的快速建模方法及验证

Efficient topology reconfiguration for NoC-based multiprocessors: A greedy-memetic algorithm

An Efficient Bottleneck Planes Exclusion Method for Reconfiguring 3D VLSI Arrays

Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect

面向Mesh网络的容错处理器阵列重构方法研究

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

A mathematical programming method for constructing the shortest interconnection VLSI arrays

An improved algorithm for accelerating reconfiguration of VLSI array

Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting

预印本

HEMERA: A Heterogeneous Memory-Centric Accelerator with Recursive Dataflow for Edge-Constrained State-Space-Duality Models Inference

研究方向