肖昊｜合肥工业大学｜学者主页

2026

High-Performance FPGA-Based LZ77 Accelerator Design With Deep-Search Capability

Hao Xiao, Xu Han, Yu Ren, Saiqin Xu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

A low-cost hardware-algorithm co-optimized architecture for sparse CNN acceleration on edge devices

Jiandong Zhu, Ning Li, Xushuai Zhu, Hao Xiao

Microelectronics Journal

DOI

2026

Auto-Mult: A Self-Optimizing Integer Multiplier via Hybrid Decomposition and Automated Parameter Search

Yan Xu, Jianbo Guo, Mengquan Li, Hao Xiao

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

2026

A Multichannel Hierarchical Hash Architecture for Low-Latency and High-Throughput Exact Matching

Xingyu Wang, Yuxuan Liu, Saiqin Xu, Hao Xiao

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

2026

A Level-Decoupled FHE Accelerator With Intra-Stage Iteration and Inter-Stage Pipelining Architecture

Jianbo Guo, Songyun Tian, Yan Xu, Hao Xiao

IEEE Transactions on Circuits and Systems I Regular Papers

DOI

2026

A High-Performance and Configurable NTT Accelerator Based on Scalable 2-D Architecture

Jianbo Guo, Jiaoyang Zhu, Hao Xiao

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2026

CSO-TFG: A Configurable Seed-Free On-the-Fly Twiddle Factor Generator for NWC-Based NTT/INTT

Tong Xu, Hao Xiao

IEEE Embedded Systems Letters

DOI

2026

Design and Implementation of a High-Throughput Hardware Accelerator for WebP Lossless Image Compression

Xu-Shuai Zhu, Hao Xiao, Hui-Yuan Wang

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2025

基于嵌套分解Winograd算法的3D-CNN硬件加速器

杨家元，刘光柱，肖昊

《复旦学报(自然科学版)》

DOI

2025

DRAM内置免校准温度传感器设计

汪于皓，肖昊

《合肥工业大学学报(自然科学版)》

2025

后量子密码中基于NTT的低成本多项式乘法器硬件设计与实现

阚瑞晨，肖昊

《合肥工业大学学报(自然科学版)》

2025

基于FPGA的轻量化霍夫变换加速器设计与实现

蒋晨鑫，肖昊，徐瀚，朱骄阳

《电子测量技术》

DOI

2025

Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme

Zhenyang Wu, Ruichen Kan, Jianbo Guo, Hao Xiao

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2025

An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload

Jianbo Guo, Tongqing Xu, Zhenyang Wu, Hao Xiao

IEEE Transactions on Very Large Scale Integration (vlsi) Systems

DOI

2024

基于低成本FPGA的深度卷积神经网络加速器设计

杨统，肖昊

《电子测量技术》

2024

基于FPGA的稀疏卷积神经网络加速器设计

李宁，肖昊

《电子测量技术》

2024

一种面积高效的双态可配置NTT硬件加速器

朱敏，肖昊

《信息网络安全》

2024

用于ICP的近似KD-Tree搜索加速器设计及FPGA实现

郑凯磊，陈强，肖昊

《合肥工业大学学报(自然科学版)》

2024

Curve25519点乘算法的高效FPGA实现

胡越，肖昊，赵延睿，刘笑帆

《合肥工业大学学报(自然科学版)》

2024

基于NTT的高效多项式乘法器设计及其FPGA实现

刘笑帆，肖昊，赵延睿，胡越

《合肥工业大学学报(自然科学版)》

2024

基于SoC的非对称数字系统算法设计与实现

姜智，肖昊

《合肥工业大学学报(自然科学版)》

2024

A high‐throughput flexible lossless compression and decompression architecture for color images

Tongqing Xu, Tan Yao, Ning Li, Junming Li, Xinlong Min, Hao Xiao

International journal of circuit theory and applications

DOI

2023

基于Winograd算法的高效神经网络加速器及FPGA实现

王帅帅，陈强，郭剑博，肖昊

《合肥工业大学学报(自然科学版)》

2023

抗量子密码中快速数论变换的硬件设计与实现

肖昊，赵延睿，胡越，刘笑帆

《信息网络安全》

2023

一种嵌入式设备固件安全更新方案

曾祥义，刘伟，肖昊

《电子科技》

2023

基于LDL算法的大规模矩阵求逆加速器设计及其FPGA实现

余浩然，肖昊

《电子科技》

2023

基于AES算法的eFlash控制器安全设计

林宇红，肖昊

《电子科技》

2023

基于轻量级分组密码算法的SoC安全存储器设计

刘伟，曾祥义，肖昊

《电子科技》

2022

面向航空目标检测的神经网络加速器设计

施立瑞，王帅帅，肖昊

《航空科学技术》

2022

改进的蒙哥马利模乘算法及FPGA实现

程碧倩，刘光柱，肖昊

《电子科技》

2022

Design and implementation of an efficient CNN accelerator for low-cost FPGAs

Yan Xu, Shuaishuai Wang, Ning Li, Hao Xiao

IEICE Electronics Express

DOI

2022

A KNN Accelerator Based on Approximate K-D Tree for ICP

Yiming Li, Kailei Zheng, Hao Xiao

International Conference on Image Processing and Media Computing (ICIPMC)

DOI

2022

FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

Hao Xiao, Sijia Yu, Biqian Cheng, Guangzhu Liu

IEICE Electronics Express

DOI

2021

A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration

Xin Cheng, Haowen Zhu, Yixuan Even Xu, Yongqiang Zhang, Hao Xiao, Zhang Zhang

Microelectronics Journal

DOI

2021

Efficient Hardware Accelerator for Compressed Sparse Deep Neural Network

Hao Xiao, Kaikai Zhao, Guangzhu Liu

IEICE Transactions on Information and Systems

DOI

2021

Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier

Hao Xiao, Yuxuan Liu, Zhenmin Li, Guangzhu Liu

IEICE Electronics Express

DOI

2018

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

Hao Xiao, Xiang Gen Yin, Ning Wu, Xin Chen, Jun Li, Xiaoxing Chen

IET Computers & Digital Techniques

DOI

2018

An Inexact Multiplier based Area-Efficient Fast Fourier Transform Processor

Xiang Gen Yin, Hao Xiao, Weiwei Cao, Shu Chen

International Conference on Advances in Energy, Environment and Chemical Science (AEECS)

DOI

精选作品

期刊论文

High-Performance FPGA-Based LZ77 Accelerator Design With Deep-Search Capability

A low-cost hardware-algorithm co-optimized architecture for sparse CNN acceleration on edge devices

Auto-Mult: A Self-Optimizing Integer Multiplier via Hybrid Decomposition and Automated Parameter Search

A Multichannel Hierarchical Hash Architecture for Low-Latency and High-Throughput Exact Matching

A Level-Decoupled FHE Accelerator With Intra-Stage Iteration and Inter-Stage Pipelining Architecture

A High-Performance and Configurable NTT Accelerator Based on Scalable 2-D Architecture

CSO-TFG: A Configurable Seed-Free On-the-Fly Twiddle Factor Generator for NWC-Based NTT/INTT

Design and Implementation of a High-Throughput Hardware Accelerator for WebP Lossless Image Compression

基于嵌套分解Winograd算法的3D-CNN硬件加速器

DRAM内置免校准温度传感器设计

后量子密码中基于NTT的低成本多项式乘法器硬件设计与实现

基于FPGA的轻量化霍夫变换加速器设计与实现

Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme

An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload

基于低成本FPGA的深度卷积神经网络加速器设计

基于FPGA的稀疏卷积神经网络加速器设计

一种面积高效的双态可配置NTT硬件加速器

用于ICP的近似KD-Tree搜索加速器设计及FPGA实现

Curve25519点乘算法的高效FPGA实现

基于NTT的高效多项式乘法器设计及其FPGA实现

基于SoC的非对称数字系统算法设计与实现

A high‐throughput flexible lossless compression and decompression architecture for color images

基于Winograd算法的高效神经网络加速器及FPGA实现

抗量子密码中快速数论变换的硬件设计与实现

一种嵌入式设备固件安全更新方案

基于LDL算法的大规模矩阵求逆加速器设计及其FPGA实现

基于AES算法的eFlash控制器安全设计

基于轻量级分组密码算法的SoC安全存储器设计

面向航空目标检测的神经网络加速器设计

改进的蒙哥马利模乘算法及FPGA实现

Design and implementation of an efficient CNN accelerator for low-cost FPGAs

A KNN Accelerator Based on Approximate K-D Tree for ICP

FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration

Efficient Hardware Accelerator for Compressed Sparse Deep Neural Network

Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

An Inexact Multiplier based Area-Efficient Fast Fourier Transform Processor

研究方向