吴春蕾｜复旦大学｜学者主页

2026

γ-ray induced improvement in radiation tolerance of heterogeneously integrated GaN BJT at the base–emitter spacing region

Junfeng Yu, Shijie Wang, Wenzhang Du, Chunlei Wu, Ji Li, D. W. Zhang, Pengcheng Yu, Hao Gu, Jiao Liang, Hong-Ping Ma, Qingchun Jon Zhang, Liang Li, Haiou Li, Xiaofeng Gu, Linna Zhao, Pengfei Wan, Wei Huang

Applied Physics Letters

DOI

2025

Bottom Isolation Design of Stacked Nanosheet Transistors From Channel Stress Engineering and Self-Heating Effects Perspectives

Boqian Shen, Chunlei Wu, Jian Ma, Hanzhi Gu, Fei Zhao, Yueyuan Yu, Yiming Xia, Jiayi Wu, Qingqing Sun, David Wei Zhang

IEEE Transactions on Electron Devices

DOI

2025

Performance Benchmark of Gate-All-Around Nanosheets Transistors Based on DTCO Simulation

Chunlei Wu, Jian Ma, Hanzhi Gu, Yueyuan Yu, Yiming Xia, Jiang Wu, Boqian Shen, Qingqing Sun, David Wei Zhang

IEEE International Conference on ASIC (ASICON)

DOI

2025

A New TCAD Simulation Framework for Strain-Aware Quantum Tunneling Current Modeling

Jian Ma, Chunlei Wu, Hanzhi Gu, Yueyuan Yu, Yiming Xia, Jiang Wu, Qingqing Sun, David Wei Zhang

IEEE International Conference on ASIC (ASICON)

DOI

2025

Cryogenic Ferroelectricity (10-298 K) of Superlattice and Solid-solution HZO Films

Yiming Xia, Chunlei Wu, Jian Ma, Hanzhi Gu, Yueyuan Yu, Jiayi Wu, Qingqing Sun, David Wei Zhang

IEEE International Conference on ASIC (ASICON)

DOI

2025

Comprehensive Analysis of Distinct TID Effects on SGT MOSFETs at On/Off States and Radiation Hardening Strategies

Junfeng Yu, Jihong Ding, H. D. Liu, Jun Ye, Xuan Xiao, Junyan Zhu, Ruihan Gao, Xiaodong Yang, Zhuang Wang, Chunlei Wu, Jiao Liang, Debin Zhang, Haiming Xu, T. F. Wang, Liang Li, Qingdong Zhang, Weiye Mo, Yang Song, Chaoran Song, Wei Huang, D. W. Zhang

IEEE Transactions on Electron Devices

DOI

2025

Steep Subthreshold Slope Transistors for Low-Power Electronics: Evolution, Challenges, and Perspectives

Rundong Jia, Chunlei Wu, Fei Liu, Qianqian Huang

IEEE Electron Devices Magazine

DOI

2025

Irradiation Hardening of SGT Based on Combined IPO Structure and Mechanism Modeling of Leakage Current Optimization

Junyan Zhu, Haonan Liu, Jun Ye, Xuan Xiao, Ruihan Gao, Junfeng Yu, Xiaodong Yang, Zhuang Wang, Chunlei Wu, Weiye Mo, Hong-Ping Ma, Qing‐Chun Zhang, Liang Li, Qingdong Zhang, T. F. Wang, Wei Huang, David Wei Zhang

IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs

DOI

2025

Degradation Mechanisms of $\beta$-Ga2O3 SBD Associated with Proton Irradiation-Induced Defects

Wenzhang Du, Yuangang Wang, Junfeng Yu, Junyan Zhu, Xinbo Zou, Liang Li, Debin Zhang, Yiwu Qiu, Xinjie Zhou, T. F. Wang, Zhihong Feng, Hong-Ping Ma, Qing‐Chun Zhang, Wei Huang, Chunlei Wu, D. W. Zhang

IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs

DOI

2025

Integrated Fast-Recovery SGT-SBR Devices with Majority Carrier Modulation During Wide Temperature Range

Jun Ye, Haonan Liu, Ruihan Gao, Xuan Xiao, Junyan Zhu, Weiye Mo, Yang Song, Xiaodong Yang, Zhuang Wang, Jiao Liang, Hong-Ping Ma, Qing‐Chun Zhang, Wei Kang Huang, Chunlei Wu, David Wei Zhang

IEEE International Symposium on Power Semiconductor Devices and ICs/Proceedings of the International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices & ICs/Proceedings of the ... International Symposium on Power Semiconductor Devices and ICs

DOI

2025

Study of Breakdown Voltage Optimization in 1100V HVIC NLDMOS Devices

Jian Ma, Shangze Wu, Jun Xi Hu, Haiyang Ling, Wenting Duan, Wensheng Qian, Chunlei Wu

DOI

2024

Bottom p-i-n Isolation Enabling GAA Nanosheet Transistor for Low-Power Applications

Chunlei Wu, Yumin Xu, Boqian Shen, Fei Zhao, Jian Ma, Hanzhi Gu, Yueyuan Yu, Min Xu, Qingqing Sun, David Wei Zhang

IEEE Transactions on Electron Devices

DOI

2024

Reverse-Biased PN Junction Isolation for Leakage Suppression and Strain Enhancement in Gate-All-Around Nanosheet FETs

Boqian Shen, Chunlei Wu, Yumin Xu, Fei Zhao, Hanzhi Gu, Jian Ma, Yueyuan Yu, Yiming Xia, Qingqing Sun, David Wei Zhang

DOI

2024

A Continuous Full Channel Potential Model for Accurate Synthetic Electricfield Calculating in Gate-All-Around Devices

Fei Zhao, Chunlei Wu, Yumin Xu, Boqian Shen, Jian Ma, Hanzhi Gu, Yueyuan Yu, Yiming Xia, Qingqing Sun, David Wei Zhang

DOI

2024

A Novel Hybrid-Channel Gate-All-Around Nanosheet Transistor for Leakage Control and Subthreshold Slope Reduction

Yumin Xu, Chunlei Wu, Boqian Shen, Fei Zhao, Hanzhi Gu, Jian Ma, Dawei Wang, Tao Liu, David Wei Zhang

DOI

2023

Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node

Dawei Wang, Xin Sun, Tao Liu, Kun Chen, Jingwen Yang, Chunlei Wu, Min Xu, Wei Zhang

Electronics

DOI

2023

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET)

Zhecheng Pan, Tao Liu, Jingwen Yang, Kun Chen, Saisheng Xu, Chunlei Wu, Min Xu, David Wei Zhang

Micromachines

DOI

2023

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

Jingwen Yang, Ziqiang Huang, Dawei Wang, Tao Liu, Xin Sun, Lewen Qian, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu, Min Xu, David Wei Zhang

Micromachines

DOI

2023

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

Jingwen Yang, Kun Chen, Dawei Wang, Tao Liu, Xin Sun, Qiang Wang, Ziqiang Huang, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu, Min Xu, David Wei Zhang

Micromachines

DOI

2023

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

Xin Sun, Dawei Wang, Lewen Qian, Tao Liu, Jingwen Yang, Kun Chen, Luyu Wang, Ziqiang Huang, Min Xu, Chen Wang, Chunlei Wu, Saisheng Xu, David Wei Zhang

Nanomaterials

DOI

2023

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

Kun Chen, Jingwen Yang, Chunlei Wu, Chen Wang, Min Xu, David Wei Zhang

IEEE Access

DOI

2022

先进CMOS制造工艺的技术演进及自主发展思考

张卫，徐敏，陈鲲，刘桃，杨静雯，孙新，黄自强，汪大伟，吴春蕾，王晨，徐赛生

《前瞻科技》

2022

High Selectivity, Low Damage ICP Etching of p-GaN over AlGaN for Normally-off p-GaN HEMTs Application

Penghao Zhang, Luyu Wang, Kaiyue Zhu, Yannan Yang, Rong Fan, Maolin Pan, Saisheng Xu, Min Xu, Chen Wang, Chunlei Wu, David Zhang

Micromachines

DOI

2022

Study of Synthetic Electric Field Effects and Quantum Confinement Effects in Extremely Scaled Gate-All-Around Tunnel FET

Yumin Xu, Boqian Shen, Dawei Wang, Tao Liu, Jingwen Yang, Kun Chen, Zhecheng Pan, Chunlei Wu, Min Xu, David Wei Zhang

IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

DOI

2022

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

Kun Chen, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, Wenchao Liu

Micromachines

DOI

2022

Investigation of Nanosheet Deformation During Channel-Release in Gate-All-Around Nanosheet Transistors

Jingwen Yang, Kun Chen, Xin Sun, Dawei Wang, Qiang Wang, Tao Liu, Ziqiang Huang, Zhecheng Pan, Saisheng Xu, Chunlei Wu, Min Xu, David Wei Zhang

China Semiconductor Technology International Conference (CSTIC)

DOI

2022

Novel Postgate Single Diffusion Break Integration in Gate-All-Around Nanosheet Transistors to Achieve Remarkable Channel Stress for N/P Current Matching

Tao Liu, Dawei Wang, Zhecheng Pan, Kun Chen, Jingwen Yang, Chunlei Wu, Saisheng Xu, Chen Wang, Min Xu, David Wei Zhang

IEEE Transactions on Electron Devices

DOI

2021

3 nm以下节点堆叠环栅器件关键技术的考虑

徐敏，张卫，陈鲲，杨静雯，刘桃，吴春蕾，王晨

《微纳电子与智能制造》

DOI

2021

Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs

Dawei Wang, Tao Liu, Xin Sun, Kun Chen, Jingwen Yang, Chunlei Wu, Min Xu, David Wei Zhang

IEEE International Conference on ASIC (ASICON)

DOI

吴春蕾

精选作品

期刊论文

γ-ray induced improvement in radiation tolerance of heterogeneously integrated GaN BJT at the base–emitter spacing region

Bottom Isolation Design of Stacked Nanosheet Transistors From Channel Stress Engineering and Self-Heating Effects Perspectives

Performance Benchmark of Gate-All-Around Nanosheets Transistors Based on DTCO Simulation

A New TCAD Simulation Framework for Strain-Aware Quantum Tunneling Current Modeling

Cryogenic Ferroelectricity (10-298 K) of Superlattice and Solid-solution HZO Films

Comprehensive Analysis of Distinct TID Effects on SGT MOSFETs at On/Off States and Radiation Hardening Strategies

Steep Subthreshold Slope Transistors for Low-Power Electronics: Evolution, Challenges, and Perspectives

Irradiation Hardening of SGT Based on Combined IPO Structure and Mechanism Modeling of Leakage Current Optimization

Degradation Mechanisms of $\beta$-Ga2O3 SBD Associated with Proton Irradiation-Induced Defects

Integrated Fast-Recovery SGT-SBR Devices with Majority Carrier Modulation During Wide Temperature Range

Study of Breakdown Voltage Optimization in 1100V HVIC NLDMOS Devices

Bottom p-i-n Isolation Enabling GAA Nanosheet Transistor for Low-Power Applications

Reverse-Biased PN Junction Isolation for Leakage Suppression and Strain Enhancement in Gate-All-Around Nanosheet FETs

A Continuous Full Channel Potential Model for Accurate Synthetic Electricfield Calculating in Gate-All-Around Devices

A Novel Hybrid-Channel Gate-All-Around Nanosheet Transistor for Leakage Control and Subthreshold Slope Reduction

Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET)

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

先进CMOS制造工艺的技术演进及自主发展思考

High Selectivity, Low Damage ICP Etching of p-GaN over AlGaN for Normally-off p-GaN HEMTs Application

Study of Synthetic Electric Field Effects and Quantum Confinement Effects in Extremely Scaled Gate-All-Around Tunnel FET

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

Investigation of Nanosheet Deformation During Channel-Release in Gate-All-Around Nanosheet Transistors

Novel Postgate Single Diffusion Break Integration in Gate-All-Around Nanosheet Transistors to Achieve Remarkable Channel Stress for N/P Current Matching

3 nm以下节点堆叠环栅器件关键技术的考虑

Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs

研究方向